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cpu/vexriscv_smp: Fix pbus width when using direct LiteDRAM interface (always 32-bit).

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This commit is contained in:
Florent Kermarrec 2022-03-28 16:03:14 +02:00
parent d214c37b76
commit e8ed297763
1 changed files with 6 additions and 2 deletions
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8
litex/soc/cores/cpu/vexriscv_smp/core.py
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@ -282,8 +282,12 @@ class VexRiscvSMP(CPU):
self.jtag_tdo = Signal() self.jtag_tdo = Signal()
self.jtag_tdi = Signal() self.jtag_tdi = Signal()
self.interrupt = Signal(32) self.interrupt = Signal(32)
self.pbus = pbus = wishbone.Interface(data_width=max(VexRiscvSMP.icache_width, VexRiscvSMP.dcache_width)) self.pbus = pbus = wishbone.Interface(data_width={
# Always 32-bit when using direct LiteDRAM interfaces.
False : 32,
# Else max of I/DCache-width.
True : max(VexRiscvSMP.icache_width, VexRiscvSMP.dcache_width),
}[VexRiscvSMP.wishbone_memory])
self.periph_buses = [pbus] # Peripheral buses (Connected to main SoC's bus). self.periph_buses = [pbus] # Peripheral buses (Connected to main SoC's bus).
self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM). self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM).