soc: Switch to litex.gen.genlib.misc.

litex/soc/cores/esc.py

@@ -7,9 +7,9 @@
 import math
 
 from migen import *
-from migen.genlib.misc import WaitTimer
 
 from litex.gen import LiteXModule
+from litex.gen.genlib.misc import WaitTimer
 
 from litex.soc.interconnect.csr import *
 from litex.soc.interconnect import wishbone

litex/soc/cores/hyperbus.py

@@ -7,7 +7,8 @@
 # SPDX-License-Identifier: BSD-2-Clause
 
 from migen import *
-from migen.genlib.misc import WaitTimer
+
+from litex.gen.genlib.misc import WaitTimer
 
 from litex.build.io import DifferentialOutput
 

litex/soc/cores/led.py

@@ -8,7 +8,8 @@
 import math
 
 from migen import *
-from migen.genlib.misc import WaitTimer
+
+from litex.gen.genlib.misc import WaitTimer
 
 from litex.soc.interconnect.csr import *
 from litex.soc.interconnect import wishbone

litex/soc/cores/prbs.py

@@ -6,10 +6,10 @@
 # SPDX-License-Identifier: BSD-2-Clause
 
 from migen import *
-from migen.genlib.misc import WaitTimer
 from migen.genlib.cdc import MultiReg
 
 from litex.gen import *
+from litex.gen.genlib.misc import WaitTimer
 
 # Constants ----------------------------------------------------------------------------------------
 

litex/soc/cores/uart.py

@@ -12,7 +12,8 @@ from math import log2
 from migen import *
 from migen.genlib.record import Record
 from migen.genlib.cdc import MultiReg
-from migen.genlib.misc import WaitTimer
+
+from litex.gen.genlib.misc import WaitTimer
 
 from litex.soc.interconnect.csr import *
 from litex.soc.interconnect.csr_eventmanager import *

litex/soc/integration/soc.py

@@ -15,10 +15,10 @@ import datetime
 from math import log2, ceil
 
 from migen import *
-from migen.genlib.misc import WaitTimer
 
 from litex.gen import colorer
 from litex.gen import LiteXModule
+from litex.gen.genlib.misc import WaitTimer
 from litex.gen.fhdl.hierarchy import LiteXHierarchyExplorer
 
 from litex.compat.soc_core import *

litex/soc/interconnect/axi/axi_common.py

@@ -9,10 +9,13 @@
 
 from migen import *
 from migen.genlib import roundrobin
-from migen.genlib.misc import WaitTimer
+
+from litex.gen.genlib.misc import WaitTimer
+
+from litex.build.generic_platform import *
 
 from litex.soc.interconnect import stream
-from litex.build.generic_platform import *
+
 
 # AXI Constants ------------------------------------------------------------------------------------
 

litex/soc/interconnect/axi/axi_full.py

@@ -9,11 +9,12 @@
 
 from migen import *
 from migen.genlib import roundrobin
-from migen.genlib.misc import WaitTimer
 
-from litex.soc.interconnect import stream
+from litex.gen.genlib.misc import WaitTimer
+
 from litex.build.generic_platform import *
 
+from litex.soc.interconnect import stream
 from litex.soc.interconnect.axi.axi_common import *
 from litex.soc.interconnect.axi.axi_stream import AXIStreamInterface
 

litex/soc/interconnect/axi/axi_lite.py

@@ -9,11 +9,12 @@
 
 from migen import *
 from migen.genlib import roundrobin
-from migen.genlib.misc import WaitTimer
 
-from litex.soc.interconnect import stream
+from litex.gen.genlib.misc import WaitTimer
+
 from litex.build.generic_platform import *
 
+from litex.soc.interconnect import stream
 from litex.soc.interconnect.axi.axi_common import *
 
 # AXI-Lite Definition ------------------------------------------------------------------------------

litex/soc/interconnect/csr_bus.py

@@ -16,10 +16,10 @@ the configuration and status registers of cores from software.
 
 from migen import *
 from migen.genlib.record import *
-from migen.genlib.misc import chooser
 from migen.util.misc import xdir
 
 from litex.gen import *
+from litex.gen.genlib.misc import chooser
 
 from litex.soc.interconnect import csr
 from litex.soc.interconnect.csr import CSRStorage

litex/soc/interconnect/wishbone.py

@@ -14,9 +14,9 @@ from math import log2
 from migen import *
 from migen.genlib import roundrobin
 from migen.genlib.record import *
-from migen.genlib.misc import split, displacer, chooser, WaitTimer
 
 from litex.gen import *
+from litex.gen.genlib.misc import split, displacer, chooser, WaitTimer
 
 from litex.build.generic_platform import *