dvisampler: add core, EDID support
This commit is contained in:
Sebastien Bourdeauducq
parent
1e7783a41e
commit
e99bafe52b
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from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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from migen.bank.description import *
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from milkymist.dvisampler.edid import EDID
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class DVISampler(Module, AutoReg):
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def __init__(self, inversions=""):
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self.clk = Signal()
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for datan in "012":
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name = "data" + str(datan)
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if datan in inversions:
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name += "_n"
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setattr(self, name, Signal(name=name))
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self.submodules.edid = EDID()
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self.sda = self.edid.sda
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self.scl = self.edid.scl
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from migen.fhdl.structure import *
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from migen.fhdl.specials import Memory, Tristate
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from migen.fhdl.module import Module
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from migen.genlib.cdc import MultiReg
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from migen.genlib.fsm import FSM
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from migen.genlib.misc import chooser
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from migen.bank.description import AutoReg
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_default_edid = [
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0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x3D, 0x17, 0x20, 0x11, 0x3E, 0x11, 0x00, 0x00,
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0x01, 0x17, 0x01, 0x03, 0x80, 0x30, 0x1B, 0x78, 0x08, 0x1D, 0xC5, 0xA4, 0x55, 0x54, 0xA0, 0x27,
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0x0C, 0x50, 0x54, 0x3F, 0xC0, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
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0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x88, 0x13, 0x20, 0x3C, 0x30, 0x58, 0x2D, 0x20, 0x58, 0x2C,
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0x45, 0x00, 0xE0, 0x0E, 0x11, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x4D, 0x31, 0x20,
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0x44, 0x56, 0x49, 0x20, 0x6D, 0x69, 0x78, 0x65, 0x72, 0x0A, 0x00, 0x00, 0x00, 0x10, 0x00, 0x32,
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0x4C, 0x1E, 0x53, 0x11, 0x00, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0x10,
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0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x00, 0x2C,
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]
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class EDID(Module, AutoReg):
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def __init__(self, default=_default_edid):
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self.scl = Signal()
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self.sda = Signal()
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self.specials.mem = Memory(8, 128, init=default)
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###
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scl_i = Signal()
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sda_i = Signal()
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sda_drv = Signal()
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_sda_drv_reg = Signal()
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_sda_i_async = Signal()
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self.sync += _sda_drv_reg.eq(sda_drv)
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self.specials += [
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MultiReg(self.scl, "ext", scl_i, "sys"),
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Tristate(self.sda, 0, _sda_drv_reg, _sda_i_async),
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MultiReg(_sda_i_async, "ext", sda_i, "sys")
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]
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# FIXME: understand what is really going on here and get rid of that workaround
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for x in range(20):
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new_scl = Signal()
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self.sync += new_scl.eq(scl_i)
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scl_i = new_scl
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#
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scl_r = Signal()
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sda_r = Signal()
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scl_rising = Signal()
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sda_rising = Signal()
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sda_falling = Signal()
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self.sync += [
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scl_r.eq(scl_i),
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sda_r.eq(sda_i)
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]
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self.comb += [
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scl_rising.eq(scl_i & ~scl_r),
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sda_rising.eq(sda_i & ~sda_r),
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sda_falling.eq(~sda_i & sda_r)
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]
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start = Signal()
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self.comb += start.eq(scl_i & sda_falling)
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din = Signal(8)
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counter = Signal(max=9)
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self.sync += [
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If(start, counter.eq(0)),
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If(scl_rising,
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If(counter == 8,
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counter.eq(0)
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).Else(
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counter.eq(counter + 1),
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din.eq(Cat(sda_i, din[:7]))
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)
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)
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]
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is_read = Signal()
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update_is_read = Signal()
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self.sync += If(update_is_read, is_read.eq(din[0]))
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offset_counter = Signal(max=128)
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oc_load = Signal()
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oc_inc = Signal()
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self.sync += [
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If(oc_load,
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offset_counter.eq(din)
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).Elif(oc_inc,
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offset_counter.eq(offset_counter + 1)
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)
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]
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rdport = self.mem.get_port()
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self.comb += rdport.adr.eq(offset_counter)
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data_bit = Signal()
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zero_drv = Signal()
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data_drv = Signal()
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self.comb += If(zero_drv, sda_drv.eq(1)).Elif(data_drv, sda_drv.eq(~data_bit))
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data_drv_en = Signal()
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data_drv_stop = Signal()
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self.sync += If(data_drv_en, data_drv.eq(1)).Elif(data_drv_stop, data_drv.eq(0))
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self.sync += If(data_drv_en, chooser(rdport.dat_r, counter, data_bit, 8, reverse=True))
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states = ["WAIT_START",
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"RCV_ADDRESS", "ACK_ADDRESS0", "ACK_ADDRESS1", "ACK_ADDRESS2",
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"RCV_OFFSET", "ACK_OFFSET0", "ACK_OFFSET1", "ACK_OFFSET2",
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"READ", "ACK_READ"]
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fsm = FSM(*states)
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self.submodules += fsm
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fsm.act(fsm.RCV_ADDRESS,
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If(counter == 8,
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If(din[1:] == 0x50,
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update_is_read.eq(1),
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fsm.next_state(fsm.ACK_ADDRESS0)
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).Else(
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fsm.next_state(fsm.WAIT_START)
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)
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)
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)
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fsm.act(fsm.ACK_ADDRESS0,
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If(~scl_i, fsm.next_state(fsm.ACK_ADDRESS1))
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)
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fsm.act(fsm.ACK_ADDRESS1,
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zero_drv.eq(1),
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If(scl_i, fsm.next_state(fsm.ACK_ADDRESS2))
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)
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fsm.act(fsm.ACK_ADDRESS2,
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zero_drv.eq(1),
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If(~scl_i,
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If(is_read,
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fsm.next_state(fsm.READ)
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).Else(
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fsm.next_state(fsm.RCV_OFFSET)
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)
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)
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)
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fsm.act(fsm.RCV_OFFSET,
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If(counter == 8,
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oc_load.eq(1),
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fsm.next_state(fsm.ACK_OFFSET0)
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)
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)
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fsm.act(fsm.ACK_OFFSET0,
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If(~scl_i, fsm.next_state(fsm.ACK_OFFSET1))
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)
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fsm.act(fsm.ACK_OFFSET1,
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zero_drv.eq(1),
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If(scl_i, fsm.next_state(fsm.ACK_OFFSET2))
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)
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fsm.act(fsm.ACK_OFFSET2,
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zero_drv.eq(1),
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If(~scl_i, fsm.next_state(fsm.RCV_ADDRESS))
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)
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fsm.act(fsm.READ,
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If(~scl_i,
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If(counter == 8,
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data_drv_stop.eq(1),
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fsm.next_state(fsm.ACK_READ)
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).Else(
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data_drv_en.eq(1)
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)
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)
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)
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fsm.act(fsm.ACK_READ,
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If(scl_rising,
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oc_inc.eq(1),
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If(sda_i,
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fsm.next_state(fsm.WAIT_START)
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).Else(
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fsm.next_state(fsm.READ)
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)
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)
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)
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for state in states:
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fsm.act(getattr(fsm, state), If(start, fsm.next_state(fsm.RCV_ADDRESS)))
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