s6ddrphy: cleanup
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da2b7aa961
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@ -67,7 +67,7 @@ def get_csr_header(csr_base, bank_array, interrupt_map):
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return r
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def get_sdram_phy_header(sdram_phy):
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if sdram_phy.phy_settings.type not in ["SDR", "DDR", "LPDDR", "DDR2"]:
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if sdram_phy.phy_settings.memtype not in ["SDR", "DDR", "LPDDR", "DDR2"]:
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raise NotImplementedError("The SDRAM PHY header generator only supports SDR, DDR, LPDDR and DDR2")
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r = "#ifndef __HW_SDRAM_PHY_H\n#define __HW_SDRAM_PHY_H\n"
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@ -129,7 +129,7 @@ static void command_p{n}(int cmd)
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cl = sdram_phy.phy_settings.cl
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if sdram_phy.phy_settings.type == "SDR":
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if sdram_phy.phy_settings.memtype == "SDR":
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bl = 1*sdram_phy.phy_settings.nphases
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mr = log2_int(bl) + (cl << 4)
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reset_dll = 1 << 8
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@ -144,7 +144,7 @@ static void command_p{n}(int cmd)
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("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
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]
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elif sdram_phy.phy_settings.type == "DDR":
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elif sdram_phy.phy_settings.memtype == "DDR":
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bl = 2*sdram_phy.phy_settings.nphases
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mr = log2_int(bl) + (cl << 4)
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emr = 0
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@ -161,7 +161,7 @@ static void command_p{n}(int cmd)
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("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
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]
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elif sdram_phy.phy_settings.type == "LPDDR":
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elif sdram_phy.phy_settings.memtype == "LPDDR":
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bl = 2*sdram_phy.phy_settings.nphases
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mr = log2_int(bl) + (cl << 4)
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emr = 0
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@ -178,7 +178,7 @@ static void command_p{n}(int cmd)
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("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
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]
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elif sdram_phy.phy_settings.type == "DDR2":
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elif sdram_phy.phy_settings.memtype == "DDR2":
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bl = 2*sdram_phy.phy_settings.nphases
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mr = log2_int(bl) + (cl << 4)
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emr = 0
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@ -7,14 +7,13 @@ from milkymist.lasmicon.refresher import *
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from milkymist.lasmicon.bankmachine import *
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from milkymist.lasmicon.multiplexer import *
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PhySettings = namedtuple("PhySettings", "type dfi_d nphases rdphase wrphase cl")
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PhySettings = namedtuple("PhySettings", "memtype dfi_d nphases rdphase wrphase cl read_latency write_latency")
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class GeomSettings(namedtuple("_GeomSettings", "bank_a row_a col_a")):
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def __init__(self, *args, **kwargs):
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self.mux_a = max(self.row_a, self.col_a)
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TimingSettings = namedtuple("TimingSettings", "tRP tRCD tWR tWTR tREFI tRFC" \
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" read_latency write_latency" \
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" req_queue_size read_time write_time")
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class LASMIcon(Module):
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@ -31,8 +30,8 @@ class LASMIcon(Module):
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dw=phy_settings.dfi_d*phy_settings.nphases,
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nbanks=2**geom_settings.bank_a,
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req_queue_size=timing_settings.req_queue_size,
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read_latency=timing_settings.read_latency+1,
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write_latency=timing_settings.write_latency+1)
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read_latency=phy_settings.read_latency+1,
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write_latency=phy_settings.write_latency+1)
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self.nrowbits = geom_settings.col_a - address_align
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###
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@ -178,7 +178,7 @@ class Multiplexer(Module, AutoCSR):
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steerer.sel[0].eq(STEER_REFRESH),
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If(~refresher.req, NextState("READ"))
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)
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fsm.delayed_enter("RTW", "WRITE", timing_settings.read_latency-1)
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fsm.delayed_enter("RTW", "WRITE", phy_settings.read_latency-1) # FIXME: reduce this, actual limit is around (cl+1)/nphases
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fsm.delayed_enter("WTR", "READ", timing_settings.tWTR-1)
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# FIXME: workaround for zero-delay loop simulation problem with Icarus Verilog
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fsm.finalize()
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@ -1,4 +1,3 @@
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#
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# 1:2 frequency-ratio DDR / LPDDR / DDR2 PHY for
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# Spartan-6
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#
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@ -12,37 +11,42 @@
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# of dfi_rddata_valid.
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#
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# This PHY only supports CAS Latency 3.
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# Read commands must be sent on phase RDPHASE.
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# Write commands must be sent on phase WRPHASE.
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#/
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# Read commands must be sent on phase 0.
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# Write commands must be sent on phase 1.
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#
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# Todo:
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# - use CSR for bitslip?
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# - add configurable CAS Latency
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# - automatically determines wrphase / rdphase / latencies according to phy_settings
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# - automatically determines wrphase / rdphase / latencies
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from migen.fhdl.std import *
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from migen.bus.dfi import *
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from migen.genlib.record import *
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def get_latencies(phy_settings):
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read_latency=5
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write_latency=0
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return read_latency, write_latency
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from milkymist import lasmicon
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class S6DDRPHY(Module):
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def __init__(self, pads, phy_settings, bitslip):
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if phy_settings.type not in ["DDR", "LPDDR", "DDR2"]:
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def __init__(self, pads, memtype, nphases, cl, bitslip):
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if memtype not in ["DDR", "LPDDR", "DDR2"]:
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raise NotImplementedError("S6DDRPHY only supports DDR, LPDDR and DDR2")
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if phy_settings.cl != 3:
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raise NotImplementedError("S6DDRPHY only supports CAS LATENCY 3 for now")
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if cl != 3:
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raise NotImplementedError("S6DDRPHY only supports CAS LATENCY 3")
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a = flen(pads.a)
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ba = flen(pads.ba)
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d = flen(pads.dq)
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nphases = phy_settings.nphases
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self.phy_settings = phy_settings
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read_latency, write_latency = get_latencies(phy_settings)
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self.phy_settings = lasmicon.PhySettings(
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memtype=memtype,
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dfi_d=2*d,
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nphases=nphases,
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rdphase=0,
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wrphase=1,
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cl=cl,
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read_latency=5,
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write_latency=0
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)
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self.dfi = Interface(a, ba, nphases*d, nphases)
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self.clk4x_wr_strb = Signal()
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@ -112,7 +116,7 @@ class S6DDRPHY(Module):
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bitslip_inc = Signal()
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sd_sys += [
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If(bitslip_cnt==bitslip,
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If(bitslip_cnt == bitslip,
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bitslip_inc.eq(0)
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).Else(
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bitslip_cnt.eq(bitslip_cnt+1),
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@ -156,7 +160,7 @@ class S6DDRPHY(Module):
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Instance.Input("S", 0),
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Instance.Output("Q", dqs_o[i])
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)
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)
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# DQS tristate cmd
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self.specials += Instance("ODDR2",
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@ -174,7 +178,7 @@ class S6DDRPHY(Module):
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Instance.Input("S", 0),
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Instance.Output("Q", dqs_t[i])
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)
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)
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# DQS tristate buffer
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self.specials += Instance("OBUFT",
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@ -182,7 +186,7 @@ class S6DDRPHY(Module):
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Instance.Input("T", dqs_t[i]),
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Instance.Output("O", pads.dqs[i])
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)
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)
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sd_sdram_half += postamble.eq(drive_dqs)
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@ -333,26 +337,26 @@ class S6DDRPHY(Module):
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Instance.Output("SHIFTOUT4"),
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)
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#
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# DQ/DQS/DM control
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#
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self.comb += drive_dq.eq(d_dfi[phy_settings.wrphase].wrdata_en)
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self.comb += drive_dq.eq(d_dfi[self.phy_settings.wrphase].wrdata_en)
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sd_sys += d_drive_dq.eq(drive_dq)
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d_dfi_wrdata_en = Signal()
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sd_sys += d_dfi_wrdata_en.eq(d_dfi[phy_settings.wrphase].wrdata_en)
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sd_sys += d_dfi_wrdata_en.eq(d_dfi[self.phy_settings.wrphase].wrdata_en)
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r_dfi_wrdata_en = Signal(2)
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sd_sdram_half += r_dfi_wrdata_en.eq(Cat(d_dfi_wrdata_en, r_dfi_wrdata_en[0]))
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self.comb += drive_dqs.eq(r_dfi_wrdata_en[1])
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rddata_sr = Signal(read_latency)
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sd_sys += rddata_sr.eq(Cat(rddata_sr[1:read_latency], d_dfi[phy_settings.rdphase].rddata_en))
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rddata_sr = Signal(self.phy_settings.read_latency)
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sd_sys += rddata_sr.eq(Cat(rddata_sr[1:self.phy_settings.read_latency],
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d_dfi[self.phy_settings.rdphase].rddata_en))
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for n, phase in enumerate(self.dfi.phases):
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self.comb += [
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phase.rddata.eq(d_dfi[n].rddata),
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phase.rddata_valid.eq(rddata_sr[0]),
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]
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]
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33
top.py
33
top.py
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@ -25,20 +25,11 @@ def ns(t, margin=True):
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t += clk_period_ns/2
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return ceil(t/clk_period_ns)
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sdram_phy = lasmicon.PhySettings(
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type="DDR",
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dfi_d=64,
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nphases=2,
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rdphase=0,
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wrphase=1,
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cl=3
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)
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sdram_geom = lasmicon.GeomSettings(
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bank_a=2,
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row_a=13,
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col_a=10
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)
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sdram_phy_read_latency, sdram_phy_write_latency = s6ddrphy.get_latencies(sdram_phy)
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sdram_timing = lasmicon.TimingSettings(
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tRP=ns(15),
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tRCD=ns(15),
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@ -46,9 +37,6 @@ sdram_timing = lasmicon.TimingSettings(
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tWTR=2,
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tREFI=ns(7800, False),
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tRFC=ns(70),
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read_latency=sdram_phy_read_latency+0,
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write_latency=sdram_phy_write_latency+0,
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req_queue_size=8,
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read_time=32,
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@ -104,10 +92,20 @@ class SoC(Module):
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}
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def __init__(self, platform, platform_name, with_memtest):
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#
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# DFI
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#
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self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), memtype="DDR", nphases=2, cl=3, bitslip=0)
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self.submodules.dfii = dfii.DFIInjector(sdram_geom.mux_a, sdram_geom.bank_a,
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self.ddrphy.phy_settings.dfi_d, self.ddrphy.phy_settings.nphases)
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self.submodules.dficon0 = dfi.Interconnect(self.dfii.master, self.ddrphy.dfi)
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#
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# LASMI
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#
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self.submodules.lasmicon = lasmicon.LASMIcon(sdram_phy, sdram_geom, sdram_timing)
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self.submodules.lasmicon = lasmicon.LASMIcon(self.ddrphy.phy_settings, sdram_geom, sdram_timing)
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self.submodules.dficon1 = dfi.Interconnect(self.lasmicon.dfi, self.dfii.slave)
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n_lasmims = 7 if with_memtest else 5
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self.submodules.lasmixbar = lasmibus.Crossbar([self.lasmicon.lasmic], n_lasmims, self.lasmicon.nrowbits)
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lasmims = list(self.lasmixbar.masters)
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@ -115,15 +113,6 @@ class SoC(Module):
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if with_memtest:
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lasmim_mtw, lasmim_mtr = lasmims.pop(), lasmims.pop()
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assert(not lasmims)
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#
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# DFI
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#
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self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), sdram_phy, 0)
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self.submodules.dfii = dfii.DFIInjector(sdram_geom.mux_a, sdram_geom.bank_a, sdram_phy.dfi_d,
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sdram_phy.nphases)
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self.submodules.dficon0 = dfi.Interconnect(self.dfii.master, self.ddrphy.dfi)
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self.submodules.dficon1 = dfi.Interconnect(self.lasmicon.dfi, self.dfii.slave)
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#
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# WISHBONE
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