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doc: remove IP

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Florent Kermarrec 2015-02-21 23:33:49 +01:00
parent 52f5955dca
commit ea7962da12
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README
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@ -18,7 +18,7 @@ PDF : www.enjoy-digital.fr/litex/litesata.pdf
LiteSATA provides a small footprint and configurable SATA gen1/2/3 core. LiteSATA provides a small footprint and configurable SATA gen1/2/3 core.
LiteSATA is part of LiteX libraries whose aims are to lower entry level of complex LiteSATA is part of LiteX libraries whose aims are to lower entry level of complex
FPGA IP cores by providing simple, elegant and efficient implementations of FPGA cores by providing simple, elegant and efficient implementations of
components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller... components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
The core uses simple and specific streaming buses and will provides in the future The core uses simple and specific streaming buses and will provides in the future

2
doc/source/docs/intro/about.rst
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@ -7,7 +7,7 @@ About LiteSATA
LiteSATA provides a small footprint and configurable SATA gen1/2/3 core. LiteSATA provides a small footprint and configurable SATA gen1/2/3 core.
LiteSATA is part of LiteX libraries whose aims is to lower entry level of complex LiteSATA is part of LiteX libraries whose aims is to lower entry level of complex
FPGA IP cores by providing simple, elegant and efficient implementations of FPGA cores by providing simple, elegant and efficient implementations of
components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller... components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
The core uses simple and specific streaming buses and will provides in the future The core uses simple and specific streaming buses and will provides in the future