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soc/cores/uart/UARTCrossover: reduce fifo_depth to 1.

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This commit is contained in:
Florent Kermarrec 2020-02-28 22:03:40 +01:00
parent 12a7528667
commit ea8563339f
1 changed files with 1 additions and 1 deletions
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2
litex/soc/cores/uart.py
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@ -272,7 +272,7 @@ class UARTCrossover(UART):
def __init__(self, **kwargs): def __init__(self, **kwargs):
assert kwargs.get("phy", None) == None assert kwargs.get("phy", None) == None
UART.__init__(self, **kwargs) UART.__init__(self, **kwargs)
self.submodules.xover = UART(tx_fifo_depth=2, rx_fifo_depth=2, rx_fifo_rx_we=True) self.submodules.xover = UART(tx_fifo_depth=1, rx_fifo_depth=1, rx_fifo_rx_we=True)
self.comb += [ self.comb += [
self.source.connect(self.xover.sink), self.source.connect(self.xover.sink),
self.xover.source.connect(self.sink) self.xover.source.connect(self.sink)