efinix: add Titanium PLL support
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@ -201,7 +201,10 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True)
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cmd += 'design.set_property("{}", pll_config, block_type="PLL")\n\n'.format(name)
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for i, clock in enumerate(block["clk_out"]):
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cmd += 'design.set_property("{}","CLKOUT{}_PHASE","{}","PLL")\n'.format(name, i, clock[2])
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if block["version"] == "V1_V2":
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cmd += 'design.set_property("{}","CLKOUT{}_PHASE","{}","PLL")\n'.format(name, i, clock[2])
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else:
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cmd += '# Phase shift needs to be implemented for PLL V3\n'
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cmd += "target_freq = {\n"
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for i, clock in enumerate(block["clk_out"]):
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@ -16,4 +16,4 @@ from litex.soc.cores.clock.lattice_ecp5 import ECP5PLL
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from litex.soc.cores.clock.lattice_nx import NXOSCA, NXPLL
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# Efinix
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from litex.soc.cores.clock.efinix_trion import TRIONPLL
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from litex.soc.cores.clock.efinix import TRIONPLL, TITANIUMPLL
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@ -16,8 +16,8 @@ class Open(Signal): pass
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# Efinix / TRIONPLL ----------------------------------------------------------------------------------
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class TRIONPLL(Module):
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nclkouts_max = 4
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def __init__(self, platform, n=0):
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nclkouts_max = 3
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def __init__(self, platform, n=0, version="V1_V2"):
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self.logger = logging.getLogger("TRIONPLL")
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self.logger.info("Creating TRIONPLL.".format())
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self.platform = platform
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@ -33,6 +33,7 @@ class TRIONPLL(Module):
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block["clk_out"] = []
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block["locked"] = self.name + "_locked"
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block["rstn"] = self.name + "_rstn"
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block["version"] = version
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self.platform.toolchain.ifacewriter.blocks.append(block)
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# Connect PLL's rstn/locked.
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@ -110,3 +111,11 @@ class TRIONPLL(Module):
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def do_finalize(self):
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pass
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# Efinix / TITANIUMPLL ----------------------------------------------------------------------------------
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class TITANIUMPLL(TRIONPLL):
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nclkouts_max = 5
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def __init__(self, platform, n=0):
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TRIONPLL.__init__(self, platform, n, version="V3")
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