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treewide: Fix "invalid escape sequence" warnings

Browse source 
Exposed with new tests.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
This commit is contained in:
Jiaxun Yang 2024-12-18 19:19:41 +00:00
parent 5855231530
commit eb1cd194a1
5 changed files with 10 additions and 10 deletions
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4
litex/soc/cores/cpu/cv32e40p/core.py
View file

@ -65,9 +65,9 @@ def add_manifest_sources(platform, manifest):
basedir = get_data_mod("cpu", "cv32e40p").data_location
with open(os.path.join(basedir, manifest), 'r') as f:
for l in f:
res = re.search('\$\{DESIGN_RTL_DIR\}/(.+)', l)
res = re.search(r'\$\{DESIGN_RTL_DIR\}/(.+)', l)
if res and not re.match('//', l):
if re.match('\+incdir\+', l):
if re.match(r'\+incdir\+', l):
platform.add_verilog_include_path(os.path.join(basedir, 'rtl', res.group(1)))
else:
platform.add_source(os.path.join(basedir, 'rtl', res.group(1)))

4
litex/soc/cores/cpu/cv32e41p/core.py
View file

@ -64,9 +64,9 @@ def add_manifest_sources(platform, manifest):
basedir = get_data_mod("cpu", "cv32e41p").data_location
with open(os.path.join(basedir, manifest), 'r') as f:
for l in f:
res = re.search('\$\{DESIGN_RTL_DIR\}/(.+)', l)
res = re.search(r'\$\{DESIGN_RTL_DIR\}/(.+)', l)
if res and not re.match('//', l):
if re.match('\+incdir\+', l):
if re.match(r'\+incdir\+', l):
platform.add_verilog_include_path(os.path.join(basedir, 'rtl', res.group(1)))
else:
platform.add_source(os.path.join(basedir, 'rtl', res.group(1)))

4
litex/soc/cores/cpu/cva6/core.py
View file

@ -44,13 +44,13 @@ def add_manifest_sources(platform, manifest):
lx_core_dir = os.path.abspath(os.path.dirname(__file__))
with open(os.path.join(manifest), 'r') as f:
for l in f:
res = re.search('\$\{(CVA6_REPO_DIR|LX_CVA6_CORE_DIR)\}/(.+)', l)
res = re.search(r'\$\{(CVA6_REPO_DIR|LX_CVA6_CORE_DIR)\}/(.+)', l)
if res and not re.match('//', l):
if res.group(1) == "LX_CVA6_CORE_DIR":
basedir = lx_core_dir
else:
basedir = cva6_dir
if re.match('\+incdir\+', l):
if re.match(r'\+incdir\+', l):
platform.add_verilog_include_path(os.path.join(basedir, res.group(2)))
else:
filename = res.group(2)

6
litex/soc/cores/cpu/openc906/core.py
View file

@ -61,9 +61,9 @@ def add_manifest_sources(platform, manifest):
basedir = os.path.join(os.environ["OPENC906_DIR"], "C906_RTL_FACTORY")
with open(os.path.join(basedir, manifest), 'r') as f:
for l in f:
res = re.search('\$\{CODE_BASE_PATH\}/(.+)', l)
if res and not re.match('//', l):
if re.match('\+incdir\+', l):
res = re.search(r'\$\{CODE_BASE_PATH\}/(.+)', l)
if res and not re.match(r'//', l):
if re.match(r'\+incdir\+', l):
platform.add_verilog_include_path(os.path.join(basedir, res.group(1)))
else:
platform.add_source(os.path.join(basedir, res.group(1)))

2
litex/soc/integration/export.py
View file

@ -98,7 +98,7 @@ def get_cpu_mak(cpu, compile_software):
for i, l in enumerate(os.popen(selected_triple + "-ar -V")):
# Version is last float reported in first line.
if i == 0:
version = float(re.findall("\d+\.\d+", l)[-1])
version = float(re.findall(r"\d+\.\d+", l)[-1])
return version
def apply_riscv_zicsr_march_workaround(flags):