build/lattice/diamond: remove ECP3 support. (ECP3 is not used and no longer interesting now that ECP5 has an open-source toolchain).
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@ -9,9 +9,9 @@ from migen.fhdl.bitcontainer import value_bits_sign
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from migen.genlib.io import *
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from migen.genlib.io import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.resetsync import AsyncResetSynchronizer
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# ECPX AsyncResetSynchronizer ----------------------------------------------------------------------
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# ECP5 AsyncResetSynchronizer ----------------------------------------------------------------------
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class LatticeECPXAsyncResetSynchronizerImpl(Module):
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class LatticeECP5AsyncResetSynchronizerImpl(Module):
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def __init__(self, cd, async_reset):
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def __init__(self, cd, async_reset):
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rst1 = Signal()
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rst1 = Signal()
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self.specials += [
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self.specials += [
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@ -28,14 +28,14 @@ class LatticeECPXAsyncResetSynchronizerImpl(Module):
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]
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]
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class LatticeECPXAsyncResetSynchronizer:
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class LatticeECP5AsyncResetSynchronizer:
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@staticmethod
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@staticmethod
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def lower(dr):
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def lower(dr):
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return LatticeECPXAsyncResetSynchronizerImpl(dr.cd, dr.async_reset)
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return LatticeECP5AsyncResetSynchronizerImpl(dr.cd, dr.async_reset)
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# ECPX DDDR Output ---------------------------------------------------------------------------------
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# ECP5 DDDR Output ---------------------------------------------------------------------------------
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class LatticeECPXDDROutputImpl(Module):
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class LatticeECP5DDROutputImpl(Module):
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def __init__(self, i1, i2, o, clk):
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def __init__(self, i1, i2, o, clk):
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self.specials += Instance("ODDRX1F",
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self.specials += Instance("ODDRX1F",
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i_SCLK = clk,
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i_SCLK = clk,
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@ -44,21 +44,21 @@ class LatticeECPXDDROutputImpl(Module):
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o_Q = o,
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o_Q = o,
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)
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)
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class LatticeECPXDDROutput:
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class LatticeECP5DDROutput:
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@staticmethod
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@staticmethod
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def lower(dr):
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def lower(dr):
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return LatticeECPXDDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk)
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return LatticeECP5DDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk)
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# ECPX Special Overrides ---------------------------------------------------------------------------
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# ECP5 Special Overrides ---------------------------------------------------------------------------
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lattice_ecpx_special_overrides = {
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lattice_ecp5_special_overrides = {
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AsyncResetSynchronizer: LatticeECPXAsyncResetSynchronizer,
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AsyncResetSynchronizer: LatticeECP5AsyncResetSynchronizer,
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DDROutput: LatticeECPXDDROutput
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DDROutput: LatticeECP5DDROutput
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}
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}
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# ECPX Trellis Tristate ----------------------------------------------------------------------------
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# ECP5 Trellis Tristate ----------------------------------------------------------------------------
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class LatticeECPXTrellisTristateImpl(Module):
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class LatticeECP5TrellisTristateImpl(Module):
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def __init__(self, io, o, oe, i):
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def __init__(self, io, o, oe, i):
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nbits, sign = value_bits_sign(io)
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nbits, sign = value_bits_sign(io)
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if nbits == 1:
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if nbits == 1:
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@ -84,17 +84,17 @@ class LatticeECPXTrellisTristateImpl(Module):
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]
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]
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class LatticeECPXTrellisTristate(Module):
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class LatticeECP5TrellisTristate(Module):
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@staticmethod
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@staticmethod
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def lower(dr):
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def lower(dr):
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return LatticeECPXTrellisTristateImpl(dr.target, dr.o, dr.oe, dr.i)
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return LatticeECP5TrellisTristateImpl(dr.target, dr.o, dr.oe, dr.i)
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# ECPX Trellis Special Overrides -------------------------------------------------------------------
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# ECP5 Trellis Special Overrides -------------------------------------------------------------------
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lattice_ecpx_trellis_special_overrides = {
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lattice_ecp5_trellis_special_overrides = {
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AsyncResetSynchronizer: LatticeECPXAsyncResetSynchronizer,
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AsyncResetSynchronizer: LatticeECP5AsyncResetSynchronizer,
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Tristate: LatticeECPXTrellisTristate,
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Tristate: LatticeECP5TrellisTristate,
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DDROutput: LatticeECPXDDROutput
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DDROutput: LatticeECP5DDROutput
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}
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}
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# iCE40 AsyncResetSynchronizer ----------------------------------------------------------------------
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# iCE40 AsyncResetSynchronizer ----------------------------------------------------------------------
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@ -146,7 +146,7 @@ class LatticeDiamondToolchain:
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"no_shreg_extract": None
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"no_shreg_extract": None
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}
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}
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special_overrides = common.lattice_ecpx_special_overrides
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special_overrides = common.lattice_ecp5_special_overrides
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def __init__(self):
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def __init__(self):
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self.false_paths = set() # FIXME: use it
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self.false_paths = set() # FIXME: use it
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@ -23,7 +23,7 @@ class LatticePlatform(GenericPlatform):
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raise ValueError("Unknown toolchain")
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raise ValueError("Unknown toolchain")
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def get_verilog(self, *args, special_overrides=dict(), **kwargs):
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def get_verilog(self, *args, special_overrides=dict(), **kwargs):
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so = dict() # No common overrides between ECPX and iCE40.
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so = dict() # No common overrides between ECP5 and iCE40.
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so.update(self.toolchain.special_overrides)
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so.update(self.toolchain.special_overrides)
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so.update(special_overrides)
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so.update(special_overrides)
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return GenericPlatform.get_verilog(self, *args, special_overrides=so,
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return GenericPlatform.get_verilog(self, *args, special_overrides=so,
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@ -168,7 +168,7 @@ class LatticeTrellisToolchain:
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"no_shreg_extract": None
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"no_shreg_extract": None
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}
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}
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special_overrides = common.lattice_ecpx_trellis_special_overrides
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special_overrides = common.lattice_ecp5_trellis_special_overrides
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def __init__(self):
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def __init__(self):
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self.yosys_template = _yosys_template
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self.yosys_template = _yosys_template
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