build/lattice/diamond: remove ECP3 support. (ECP3 is not used and no longer interesting now that ECP5 has an open-source toolchain).

This commit is contained in:
Florent Kermarrec 2020-03-24 19:36:57 +01:00
parent bba5f1828b
commit eb64169521
4 changed files with 24 additions and 24 deletions

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@ -9,9 +9,9 @@ from migen.fhdl.bitcontainer import value_bits_sign
from migen.genlib.io import * from migen.genlib.io import *
from migen.genlib.resetsync import AsyncResetSynchronizer from migen.genlib.resetsync import AsyncResetSynchronizer
# ECPX AsyncResetSynchronizer ---------------------------------------------------------------------- # ECP5 AsyncResetSynchronizer ----------------------------------------------------------------------
class LatticeECPXAsyncResetSynchronizerImpl(Module): class LatticeECP5AsyncResetSynchronizerImpl(Module):
def __init__(self, cd, async_reset): def __init__(self, cd, async_reset):
rst1 = Signal() rst1 = Signal()
self.specials += [ self.specials += [
@ -28,14 +28,14 @@ class LatticeECPXAsyncResetSynchronizerImpl(Module):
] ]
class LatticeECPXAsyncResetSynchronizer: class LatticeECP5AsyncResetSynchronizer:
@staticmethod @staticmethod
def lower(dr): def lower(dr):
return LatticeECPXAsyncResetSynchronizerImpl(dr.cd, dr.async_reset) return LatticeECP5AsyncResetSynchronizerImpl(dr.cd, dr.async_reset)
# ECPX DDDR Output --------------------------------------------------------------------------------- # ECP5 DDDR Output ---------------------------------------------------------------------------------
class LatticeECPXDDROutputImpl(Module): class LatticeECP5DDROutputImpl(Module):
def __init__(self, i1, i2, o, clk): def __init__(self, i1, i2, o, clk):
self.specials += Instance("ODDRX1F", self.specials += Instance("ODDRX1F",
i_SCLK = clk, i_SCLK = clk,
@ -44,21 +44,21 @@ class LatticeECPXDDROutputImpl(Module):
o_Q = o, o_Q = o,
) )
class LatticeECPXDDROutput: class LatticeECP5DDROutput:
@staticmethod @staticmethod
def lower(dr): def lower(dr):
return LatticeECPXDDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk) return LatticeECP5DDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk)
# ECPX Special Overrides --------------------------------------------------------------------------- # ECP5 Special Overrides ---------------------------------------------------------------------------
lattice_ecpx_special_overrides = { lattice_ecp5_special_overrides = {
AsyncResetSynchronizer: LatticeECPXAsyncResetSynchronizer, AsyncResetSynchronizer: LatticeECP5AsyncResetSynchronizer,
DDROutput: LatticeECPXDDROutput DDROutput: LatticeECP5DDROutput
} }
# ECPX Trellis Tristate ---------------------------------------------------------------------------- # ECP5 Trellis Tristate ----------------------------------------------------------------------------
class LatticeECPXTrellisTristateImpl(Module): class LatticeECP5TrellisTristateImpl(Module):
def __init__(self, io, o, oe, i): def __init__(self, io, o, oe, i):
nbits, sign = value_bits_sign(io) nbits, sign = value_bits_sign(io)
if nbits == 1: if nbits == 1:
@ -84,17 +84,17 @@ class LatticeECPXTrellisTristateImpl(Module):
] ]
class LatticeECPXTrellisTristate(Module): class LatticeECP5TrellisTristate(Module):
@staticmethod @staticmethod
def lower(dr): def lower(dr):
return LatticeECPXTrellisTristateImpl(dr.target, dr.o, dr.oe, dr.i) return LatticeECP5TrellisTristateImpl(dr.target, dr.o, dr.oe, dr.i)
# ECPX Trellis Special Overrides ------------------------------------------------------------------- # ECP5 Trellis Special Overrides -------------------------------------------------------------------
lattice_ecpx_trellis_special_overrides = { lattice_ecp5_trellis_special_overrides = {
AsyncResetSynchronizer: LatticeECPXAsyncResetSynchronizer, AsyncResetSynchronizer: LatticeECP5AsyncResetSynchronizer,
Tristate: LatticeECPXTrellisTristate, Tristate: LatticeECP5TrellisTristate,
DDROutput: LatticeECPXDDROutput DDROutput: LatticeECP5DDROutput
} }
# iCE40 AsyncResetSynchronizer ---------------------------------------------------------------------- # iCE40 AsyncResetSynchronizer ----------------------------------------------------------------------

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@ -146,7 +146,7 @@ class LatticeDiamondToolchain:
"no_shreg_extract": None "no_shreg_extract": None
} }
special_overrides = common.lattice_ecpx_special_overrides special_overrides = common.lattice_ecp5_special_overrides
def __init__(self): def __init__(self):
self.false_paths = set() # FIXME: use it self.false_paths = set() # FIXME: use it

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@ -23,7 +23,7 @@ class LatticePlatform(GenericPlatform):
raise ValueError("Unknown toolchain") raise ValueError("Unknown toolchain")
def get_verilog(self, *args, special_overrides=dict(), **kwargs): def get_verilog(self, *args, special_overrides=dict(), **kwargs):
so = dict() # No common overrides between ECPX and iCE40. so = dict() # No common overrides between ECP5 and iCE40.
so.update(self.toolchain.special_overrides) so.update(self.toolchain.special_overrides)
so.update(special_overrides) so.update(special_overrides)
return GenericPlatform.get_verilog(self, *args, special_overrides=so, return GenericPlatform.get_verilog(self, *args, special_overrides=so,

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@ -168,7 +168,7 @@ class LatticeTrellisToolchain:
"no_shreg_extract": None "no_shreg_extract": None
} }
special_overrides = common.lattice_ecpx_trellis_special_overrides special_overrides = common.lattice_ecp5_trellis_special_overrides
def __init__(self): def __init__(self):
self.yosys_template = _yosys_template self.yosys_template = _yosys_template