new MigLa Class, simplify & clean up
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dbc208395d
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eba6a2c764
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@ -25,11 +25,11 @@ record_size = 1024
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csr = Uart2Spi(1,115200)
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# Csr Addr
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MIGIO0_ADDR = 0x0000
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MIGIO_ADDR = 0x0000
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# MigScope Configuration
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# migIo
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migIo0 = migIo.MigIo(MIGIO0_ADDR, 8, "IO", csr)
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migIo0 = migIo.MigIo(MIGIO_ADDR, 8, "IO", csr)
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def led_anim0():
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for i in range(10):
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@ -8,7 +8,7 @@ from migen.bank.description import *
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import sys
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sys.path.append("../../../")
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from migScope import trigger, recorder, migIo
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from migScope import trigger, recorder, migIo, migLa
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from migScope.tools.truthtable import *
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from migScope.tools.vcd import *
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import spi2Csr
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@ -25,22 +25,21 @@ dat_width = 16
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record_size = 4096
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# Csr Addr
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MIGIO0_ADDR = 0x0000
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TRIGGER_ADDR = 0x0200
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RECORDER_ADDR = 0x0400
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MIGIO_ADDR = 0x0000
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MIGLA_ADDR = 0x0200
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csr = Uart2Spi(1,115200)
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csr = Uart2Spi(1,115200,debug=False)
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# MigScope Configuration
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# migIo
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migIo0 = migIo.MigIo(MIGIO0_ADDR, 8, "IO",csr)
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migIo0 = migIo.MigIo(MIGIO_ADDR, 8, "IO",csr)
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# Trigger
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term0 = trigger.Term(trig_width)
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trigger0 = trigger.Trigger(TRIGGER_ADDR, trig_width, dat_width, [term0], csr)
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trigger0 = trigger.Trigger(trig_width, [term0])
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recorder0 = recorder.Recorder(dat_width, record_size)
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# Recorder
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recorder0 = recorder.Recorder(RECORDER_ADDR, dat_width, record_size, csr)
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migLa0 = migLa.MigLa(MIGLA_ADDR, trigger0, recorder0, csr)
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#==============================================================================
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# T E S T M I G L A
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@ -53,19 +52,19 @@ def capture():
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global recorder0
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global dat_vcd
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sum_tt = gen_truth_table("term0")
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trigger0.sum.write(sum_tt)
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recorder0.reset()
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recorder0.offset(0)
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recorder0.arm()
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migLa0.trig.sum.write(sum_tt)
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migLa0.rec.reset()
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migLa0.rec.offset(0)
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migLa0.rec.arm()
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print("-Recorder [Armed]")
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print("-Waiting Trigger...", end = ' ')
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while(not recorder0.is_done()):
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while(not migLa0.rec.is_done()):
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time.sleep(0.1)
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print("[Done]")
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print("-Receiving Data...", end = ' ')
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sys.stdout.flush()
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dat_vcd += recorder0.read(1024)
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dat_vcd += migLa0.rec.read(1024)
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print("[Done]")
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print("Capturing Ramp..")
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@ -42,7 +42,7 @@ from migen.bank.description import *
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import sys
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sys.path.append("../../")
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from migScope import trigger, recorder, migIo
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from migScope import trigger, recorder, migIo, migLa
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import spi2Csr
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from timings import *
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@ -68,8 +68,7 @@ record_size = 4096
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# Csr Addr
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MIGIO_ADDR = 0x0000
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TRIGGER_ADDR = 0x0200
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RECORDER_ADDR = 0x0400
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MIGLA_ADDR = 0x0200
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#==============================================================================
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# M I S C O P E E X A M P L E
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@ -79,13 +78,12 @@ def get():
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# migIo
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migIo0 = migIo.MigIo(MIGIO_ADDR, 8, "IO")
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# Trigger
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# migLa
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term0 = trigger.Term(trig_width)
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trigger0 = trigger.Trigger(trig_width, [term0])
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recorder0 = recorder.Recorder(dat_width, record_size)
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trigger0 = trigger.Trigger(TRIGGER_ADDR, trig_width, dat_width, [term0])
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# Recorder
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recorder0 = recorder.Recorder(RECORDER_ADDR, dat_width, record_size)
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migLa0 = migLa.MigLa(MIGLA_ADDR, trigger0, recorder0)
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# Spi2Csr
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spi2csr0 = spi2Csr.Spi2Csr(16,8)
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@ -94,8 +92,8 @@ def get():
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csrcon0 = csr.Interconnect(spi2csr0.csr,
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[
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migIo0.bank.interface,
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trigger0.bank.interface,
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recorder0.bank.interface
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migLa0.trig.bank.interface,
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migLa0.rec.bank.interface
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])
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comb = []
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sync = []
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@ -146,19 +144,12 @@ def get():
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comb += [led0.eq(migIo0.o[:8])]
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# Dat / Trig Bus
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# MigLa0 input
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comb += [
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trigger0.in_trig.eq(sig_gen),
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trigger0.in_dat.eq(sig_gen)
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migLa0.in_trig.eq(sig_gen),
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migLa0.in_dat.eq(sig_gen)
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]
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# Trigger --> Recorder
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comb += [
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recorder0.trig_dat.eq(trigger0.dat),
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recorder0.trig_hit.eq(trigger0.hit)
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]
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# HouseKeeping
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cd_in = ClockDomain("in")
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in_rst_n = Signal()
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@ -25,11 +25,11 @@ record_size = 1024
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csr = Uart2Spi(1,115200)
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# Csr Addr
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MIGIO0_ADDR = 0x0000
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MIGIO_ADDR = 0x0000
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# MigScope Configuration
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# migIo
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migIo0 = migIo.MigIo(MIGIO0_ADDR, 8, "IO", csr)
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migIo0 = migIo.MigIo(MIGIO_ADDR, 8, "IO", csr)
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def led_anim0():
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for i in range(10):
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@ -8,7 +8,7 @@ from migen.bank.description import *
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import sys
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sys.path.append("../../../")
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from migScope import trigger, recorder, migIo
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from migScope import trigger, recorder, migIo, migLa
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from migScope.tools.truthtable import *
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from migScope.tools.vcd import *
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import spi2Csr
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@ -25,22 +25,21 @@ dat_width = 16
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record_size = 4096
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# Csr Addr
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MIGIO0_ADDR = 0x0000
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TRIGGER_ADDR = 0x0200
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RECORDER_ADDR = 0x0400
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MIGIO_ADDR = 0x0000
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MIGLA_ADDR = 0x0200
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csr = Uart2Spi(1,115200)
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csr = Uart2Spi(1,115200,debug=False)
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# MigScope Configuration
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# migIo
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migIo0 = migIo.MigIo(MIGIO0_ADDR, 8, "IO",csr)
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migIo0 = migIo.MigIo(MIGIO_ADDR, 8, "IO",csr)
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# Trigger
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term0 = trigger.Term(trig_width)
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trigger0 = trigger.Trigger(TRIGGER_ADDR, trig_width, dat_width, [term0], csr)
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trigger0 = trigger.Trigger(trig_width, [term0])
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recorder0 = recorder.Recorder(dat_width, record_size)
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# Recorder
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recorder0 = recorder.Recorder(RECORDER_ADDR, dat_width, record_size, csr)
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migLa0 = migLa.MigLa(MIGLA_ADDR, trigger0, recorder0, csr)
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#==============================================================================
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# T E S T M I G L A
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@ -53,19 +52,19 @@ def capture():
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global recorder0
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global dat_vcd
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sum_tt = gen_truth_table("term0")
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trigger0.sum.write(sum_tt)
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recorder0.reset()
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recorder0.offset(0)
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recorder0.arm()
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migLa0.trig.sum.write(sum_tt)
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migLa0.rec.reset()
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migLa0.rec.offset(0)
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migLa0.rec.arm()
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print("-Recorder [Armed]")
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print("-Waiting Trigger...", end = ' ')
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while(not recorder0.is_done()):
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while(not migLa0.rec.is_done()):
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time.sleep(0.1)
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print("[Done]")
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print("-Receiving Data...", end = ' ')
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sys.stdout.flush()
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dat_vcd += recorder0.read(1024)
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dat_vcd += migLa0.rec.read(1024)
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print("[Done]")
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print("Capturing Ramp..")
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@ -1,5 +1,5 @@
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$date
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2012-09-16 01:27
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2012-09-17 17:00
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$end
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$version
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miscope VCD dump
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@ -42,7 +42,7 @@ from migen.bank.description import *
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import sys
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sys.path.append("../../")
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from migScope import trigger, recorder, migIo
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from migScope import trigger, recorder, migIo, migLa
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import spi2Csr
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from timings import *
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@ -68,8 +68,7 @@ record_size = 4096
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# Csr Addr
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MIGIO_ADDR = 0x0000
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TRIGGER_ADDR = 0x0200
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RECORDER_ADDR = 0x0400
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MIGLA_ADDR = 0x0200
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#==============================================================================
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# M I S C O P E E X A M P L E
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@ -79,13 +78,12 @@ def get():
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# migIo
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migIo0 = migIo.MigIo(MIGIO_ADDR, 8, "IO")
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# Trigger
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# migLa
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term0 = trigger.Term(trig_width)
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trigger0 = trigger.Trigger(trig_width, [term0])
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recorder0 = recorder.Recorder(dat_width, record_size)
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trigger0 = trigger.Trigger(TRIGGER_ADDR, trig_width, dat_width, [term0])
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# Recorder
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recorder0 = recorder.Recorder(RECORDER_ADDR, dat_width, record_size)
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migLa0 = migLa.MigLa(MIGLA_ADDR, trigger0, recorder0)
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# Spi2Csr
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spi2csr0 = spi2Csr.Spi2Csr(16,8)
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csrcon0 = csr.Interconnect(spi2csr0.csr,
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[
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migIo0.bank.interface,
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trigger0.bank.interface,
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recorder0.bank.interface
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migLa0.trig.bank.interface,
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migLa0.rec.bank.interface
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])
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comb = []
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sync = []
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@ -149,19 +147,12 @@ def get():
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sw0 = Signal(BV(8))
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comb += [migIo0.i.eq(sw0)]
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# Dat / Trig Bus
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# MigLa0 input
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comb += [
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trigger0.in_trig.eq(sig_gen),
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trigger0.in_dat.eq(sig_gen)
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migLa0.in_trig.eq(sig_gen),
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migLa0.in_dat.eq(sig_gen)
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]
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# Trigger --> Recorder
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comb += [
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recorder0.trig_dat.eq(trigger0.dat),
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recorder0.trig_hit.eq(trigger0.hit)
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]
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# HouseKeeping
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cd_in = ClockDomain("in")
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in_rst_n = Signal()
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@ -5,6 +5,9 @@ from migen.bank.description import *
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class MigIo:
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#
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# Definition
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#
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def __init__(self,address, width, mode = "IO", interface=None):
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self.address = address
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self.width = width
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self.oreg.field.r.name_override = "ouptuts"
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self.bank = csrgen.Bank([self.oreg, self.ireg], address=self.address)
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def write(self, data):
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self.interface.write_n(self.address, data, self.width)
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def read(self):
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r = self.interface.read_n(self.address + self.words, self.width)
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return r
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def get_fragment(self):
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comb = []
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if "I" in self.mode:
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if "O" in self.mode:
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comb += [self.o.eq(self.oreg.field.r)]
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return Fragment(comb=comb) + self.bank.get_fragment()
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#
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#Driver
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#
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def write(self, data):
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self.interface.write_n(self.address, data, self.width)
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def read(self):
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r = self.interface.read_n(self.address + self.words, self.width)
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return r
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@ -0,0 +1,36 @@
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from migen.fhdl.structure import *
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from migen.bus import csr
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from migen.bank import description, csrgen
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from migen.bank.description import *
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import sys
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sys.path.append("../")
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from migScope import trigger, recorder
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class MigLa:
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def __init__(self,address, trig, rec, interface=None):
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self.address = address
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self.trig = trig
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self.rec = rec
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self.interface = interface
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self.in_trig = Signal(BV(self.trig.trig_width))
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self.in_dat = Signal(BV(self.trig.trig_width))
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self.trig.set_address(self.address)
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self.rec.set_address(self.address + 0x0200)
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self.trig.set_interface(self.interface)
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self.rec.set_interface(self.interface)
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def get_fragment(self):
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comb = []
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comb += [
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self.trig.in_trig.eq(self.in_trig),
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]
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comb += [
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self.rec.trig_dat.eq(self.in_dat),
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self.rec.trig_hit.eq(self.trig.hit)
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]
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return Fragment(comb=comb)
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@ -5,6 +5,9 @@ from migen.bank.description import *
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from migen.corelogic.misc import optree
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class Storage:
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#
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# Definition
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#
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def __init__(self, width, depth):
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self.width = width
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self.depth = depth
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return Fragment(comb=comb, sync=sync, memories=memories)
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class Sequencer:
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#
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# Definition
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#
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def __init__(self,depth):
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self.depth = depth
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self.depth_width = bits_for(self.depth)
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return Fragment(comb=comb, sync=sync)
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class Recorder:
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def __init__(self,address, width, depth, interface = None):
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#
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# Definition
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#
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def __init__(self, width, depth, address = 0x0000, interface = None):
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self.address = address
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self.width = width
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self.depth = depth
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self._get = RegisterField("get", reset=0)
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self._get_dat = RegisterField("get_dat", self.width, reset=1, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
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regs = [self._rst, self._arm, self._done,
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self.regs = [self._rst, self._arm, self._done,
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self._size, self._offset,
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self._get, self._get_dat]
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self.bank = csrgen.Bank(regs,address=self.address)
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self.bank = csrgen.Bank(self.regs,address=self.address)
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# Trigger Interface
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self.trig_hit = Signal()
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self.trig_dat = Signal(BV(self.width))
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def reset(self):
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self.interface.write(self.address + 0x00, 1)
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self.interface.write(self.address + 0x00, 0)
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def set_address(self, address):
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self.address = address
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self.bank = csrgen.Bank(self.regs,address=self.address)
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def arm(self):
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self.interface.write(self.address + 0x01, 1)
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self.interface.write(self.address + 0x01, 0)
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def is_done(self):
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return self.interface.read(self.address + 0x02) == 1
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def size(self, dat):
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self.size = dat
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self.interface.write_n(self.address + 0x03, dat, 16)
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def offset(self, dat):
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self.interface.write_n(self.address + 0x05, dat, 16)
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def read(self, size):
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r = []
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for i in range(size):
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self.interface.write(self.address+7, 1)
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self.interface.write(self.address+7, 0)
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r.append(self.interface.read_n(self.address+8,self.width))
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return r
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def set_interface(self, interface):
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self.interface = interface
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def get_fragment(self):
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comb = []
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return self.bank.get_fragment()+\
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self.storage.get_fragment()+self.sequencer.get_fragment()+\
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Fragment(comb=comb, sync=sync)
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#
|
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#Driver
|
||||
#
|
||||
def reset(self):
|
||||
self.interface.write(self.address + 0x00, 1)
|
||||
self.interface.write(self.address + 0x00, 0)
|
||||
|
||||
def arm(self):
|
||||
self.interface.write(self.address + 0x01, 1)
|
||||
self.interface.write(self.address + 0x01, 0)
|
||||
|
||||
def is_done(self):
|
||||
return self.interface.read(self.address + 0x02) == 1
|
||||
|
||||
def size(self, dat):
|
||||
self.size = dat
|
||||
self.interface.write_n(self.address + 0x03, dat, 16)
|
||||
|
||||
def offset(self, dat):
|
||||
self.interface.write_n(self.address + 0x05, dat, 16)
|
||||
|
||||
def read(self, size):
|
||||
r = []
|
||||
for i in range(size):
|
||||
self.interface.write(self.address+7, 1)
|
||||
self.interface.write(self.address+7, 0)
|
||||
r.append(self.interface.read_n(self.address+8,self.width))
|
||||
return r
|
||||
|
|
|
@ -5,6 +5,9 @@ from migen.bank.description import *
|
|||
from migen.corelogic.misc import optree
|
||||
|
||||
class Term:
|
||||
#
|
||||
# Definition
|
||||
#
|
||||
def __init__(self, width, pipe=False):
|
||||
self.width = width
|
||||
self.pipe = pipe
|
||||
|
@ -19,9 +22,6 @@ class Term:
|
|||
self.t = Signal(BV(self.width))
|
||||
self.o = Signal()
|
||||
|
||||
def write(self, dat):
|
||||
self.interface.write_n(self.reg_base, dat ,self.width)
|
||||
|
||||
def get_fragment(self):
|
||||
frag = [
|
||||
self.o.eq(self.i==self.t)
|
||||
|
@ -35,8 +35,16 @@ class Term:
|
|||
comb = []
|
||||
comb += [self.t.eq(reg.field.r[0*self.width:1*self.width])]
|
||||
return comb
|
||||
#
|
||||
#Driver
|
||||
#
|
||||
def write(self, dat):
|
||||
self.interface.write_n(self.reg_base, dat ,self.width)
|
||||
|
||||
class RangeDetector:
|
||||
#
|
||||
# Definition
|
||||
#
|
||||
def __init__(self, width, pipe=False):
|
||||
self.width = width
|
||||
self.pipe = pipe
|
||||
|
@ -52,12 +60,6 @@ class RangeDetector:
|
|||
self.high = Signal(BV(self.width))
|
||||
self.o = Signal()
|
||||
|
||||
def write_low(self, dat):
|
||||
self.interface.write_n(self.reg_base, dat ,self.width)
|
||||
|
||||
def write_high(self, dat):
|
||||
self.interface.write_n(self.reg_base + self.words, dat ,self.width)
|
||||
|
||||
def get_fragment(self):
|
||||
frag = [
|
||||
self.o.eq((self.i >= self.low) & ((self.i <= self.high)))
|
||||
|
@ -72,8 +74,19 @@ class RangeDetector:
|
|||
comb += [self.low.eq(reg.field.r[0*self.width:1*self.width])]
|
||||
comb += [self.low.eq(reg.field.r[1*self.width:2*self.width])]
|
||||
return comb
|
||||
#
|
||||
#Driver
|
||||
#
|
||||
def write_low(self, dat):
|
||||
self.interface.write_n(self.reg_base, dat ,self.width)
|
||||
|
||||
def write_high(self, dat):
|
||||
self.interface.write_n(self.reg_base + self.words, dat ,self.width)
|
||||
|
||||
class EdgeDetector:
|
||||
#
|
||||
# Definition
|
||||
#
|
||||
def __init__(self, width, pipe=False, mode = "RFB"):
|
||||
self.width = width
|
||||
self.pipe = pipe
|
||||
|
@ -97,22 +110,6 @@ class EdgeDetector:
|
|||
self.bo = Signal()
|
||||
self.o = Signal()
|
||||
|
||||
def write_r(self, dat):
|
||||
self.interface.write_n(self.reg_base, dat ,self.width)
|
||||
|
||||
def write_f(self, dat):
|
||||
offset = 0
|
||||
if "R" in self.mode:
|
||||
offset += self.words
|
||||
self.interface.write_n(self.reg_base + offset, dat ,self.width)
|
||||
|
||||
def write_b(self, dat):
|
||||
if "R" in self.mode:
|
||||
offset += self.words
|
||||
if "F" in self.mode:
|
||||
offset += self.words
|
||||
self.interface.write_n(self.reg_base + offset, dat ,self.width)
|
||||
|
||||
def get_fragment(self):
|
||||
comb = []
|
||||
sync = []
|
||||
|
@ -163,7 +160,29 @@ class EdgeDetector:
|
|||
i += 1
|
||||
return comb
|
||||
|
||||
#
|
||||
#Driver
|
||||
#
|
||||
def write_r(self, dat):
|
||||
self.interface.write_n(self.reg_base, dat ,self.width)
|
||||
|
||||
def write_f(self, dat):
|
||||
offset = 0
|
||||
if "R" in self.mode:
|
||||
offset += self.words
|
||||
self.interface.write_n(self.reg_base + offset, dat ,self.width)
|
||||
|
||||
def write_b(self, dat):
|
||||
if "R" in self.mode:
|
||||
offset += self.words
|
||||
if "F" in self.mode:
|
||||
offset += self.words
|
||||
self.interface.write_n(self.reg_base + offset, dat ,self.width)
|
||||
|
||||
class Timer:
|
||||
#
|
||||
# Definition
|
||||
#
|
||||
def __init__(self, width):
|
||||
self.width = width
|
||||
self.interface = None
|
||||
|
@ -212,6 +231,9 @@ class Timer:
|
|||
return Fragment(comb, sync)
|
||||
|
||||
class Sum:
|
||||
#
|
||||
# Definition
|
||||
#
|
||||
def __init__(self,width=4,pipe=False):
|
||||
self.width = width
|
||||
self.pipe = pipe
|
||||
|
@ -233,15 +255,6 @@ class Sum:
|
|||
|
||||
self._mem = Memory(1, 2**self.width, self._lut_port, self._prog_port)
|
||||
|
||||
def write(self, truth_table):
|
||||
for i in range(len(truth_table)):
|
||||
val = truth_table[i]
|
||||
we = 1<<17
|
||||
dat = val<<16
|
||||
addr = i
|
||||
self.interface.write_n(self.reg_base, we + dat + addr,self.reg_size)
|
||||
self.interface.write_n(self.reg_base, dat + addr, self.reg_size)
|
||||
|
||||
def get_fragment(self):
|
||||
comb = []
|
||||
sync = []
|
||||
|
@ -261,20 +274,32 @@ class Sum:
|
|||
]
|
||||
return comb
|
||||
|
||||
#
|
||||
#Driver
|
||||
#
|
||||
def write(self, truth_table):
|
||||
for i in range(len(truth_table)):
|
||||
val = truth_table[i]
|
||||
we = 1<<17
|
||||
dat = val<<16
|
||||
addr = i
|
||||
self.interface.write_n(self.reg_base, we + dat + addr,self.reg_size)
|
||||
self.interface.write_n(self.reg_base, dat + addr, self.reg_size)
|
||||
|
||||
class Trigger:
|
||||
def __init__(self,address, trig_width, dat_width, ports, interface = None):
|
||||
#
|
||||
# Definition
|
||||
#
|
||||
def __init__(self, trig_width, ports, address = 0x0000, interface = None):
|
||||
self.address = address
|
||||
self.trig_width = trig_width
|
||||
self.dat_width = dat_width
|
||||
self.ports = ports
|
||||
self.interface = interface
|
||||
self.sum = Sum(len(self.ports))
|
||||
|
||||
self.in_trig = Signal(BV(self.trig_width))
|
||||
self.in_dat = Signal(BV(self.dat_width))
|
||||
|
||||
self.hit = Signal()
|
||||
self.dat = Signal(BV(self.dat_width))
|
||||
|
||||
# Update port reg_name
|
||||
for i in range(len(self.ports)):
|
||||
|
@ -286,19 +311,28 @@ class Trigger:
|
|||
access_bus=WRITE_ONLY, access_dev=READ_ONLY))
|
||||
self.sum_reg = RegisterField(self.sum.reg_name, self.sum.reg_size, reset=0, access_bus=WRITE_ONLY, access_dev=READ_ONLY)
|
||||
|
||||
regs = []
|
||||
self.regs = []
|
||||
objects = self.__dict__
|
||||
for object in sorted(objects):
|
||||
if "_reg" in object:
|
||||
regs.append(objects[object])
|
||||
self.bank = csrgen.Bank(regs,address=self.address)
|
||||
self.regs.append(objects[object])
|
||||
self.bank = csrgen.Bank(self.regs,address=self.address)
|
||||
|
||||
# Update base addr
|
||||
self.set_address(self.address)
|
||||
|
||||
# Update interface
|
||||
self.set_interface(self.interface)
|
||||
|
||||
def set_address(self, address):
|
||||
self.address = address
|
||||
self.bank = csrgen.Bank(self.regs,address=self.address)
|
||||
for port in self.ports:
|
||||
port.reg_base = self.bank.get_base(port.reg_name)
|
||||
self.sum.reg_base = self.bank.get_base(self.sum.reg_name)
|
||||
|
||||
# Update interface
|
||||
def set_interface(self, interface):
|
||||
self.interface = interface
|
||||
for port in self.ports:
|
||||
port.interface = self.interface
|
||||
self.sum.interface = self.interface
|
||||
|
@ -320,7 +354,6 @@ class Trigger:
|
|||
frag += self.sum.get_fragment()
|
||||
for port in self.ports:
|
||||
frag += port.get_fragment()
|
||||
comb+= [self.dat.eq(self.in_dat)]
|
||||
|
||||
#Connect Registers
|
||||
for port in self.ports:
|
||||
|
|
Loading…
Reference in New Issue