Rename litex-data-XXX-YYY to pythondata-XXX-YYY
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@ -1,6 +1,3 @@
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# https://packaging.python.org/guides/packaging-namespace-packages/#pkgutil-style-namespace-packages
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__path__ = __import__('pkgutil').extend_path(__path__, __name__)
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import sys
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import sys
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# retro-compat 2019-09-30
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# retro-compat 2019-09-30
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@ -12,3 +9,20 @@ from litex.soc.integration import export
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sys.modules["litex.soc.integration.cpu_interface"] = export
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sys.modules["litex.soc.integration.cpu_interface"] = export
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from litex.tools.litex_client import RemoteClient
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from litex.tools.litex_client import RemoteClient
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def get_data_mod(data_type, data_name):
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"""Get the pythondata-{}-{} module or raise a useful error message."""
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imp = "import pythondata_{}_{} as dm".format(data_type, data_name)
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try:
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l = {}
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exec(imp, {}, l)
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dm = l['dm']
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return dm
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except ImportError as e:
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raise ImportError("""\
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pythondata-{dt}-{dn} module not installed! Unable to use {dn} {dt}.
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{e}
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You can install this by running;
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pip install git+https://github.com/litex-hub/pythondata-{dt}-{dn}.git
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""".format(dt=data_type, dn=data_name, e=e))
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@ -1,2 +0,0 @@
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# https://packaging.python.org/guides/packaging-namespace-packages/#pkgutil-style-namespace-packages
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__path__ = __import__('pkgutil').extend_path(__path__, __name__)
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@ -1,15 +0,0 @@
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def find_data(data_type, data_name):
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imp = "from litex.data.{} import {} as dm".format(data_type, data_name)
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try:
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l = {}
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exec(imp, {}, l)
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dm = l['dm']
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return dm.data_location
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except ImportError as e:
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raise ImportError("""\
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litex-data-{dt}-{dn} module not installed! Unable to use {dn} {dt}.
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{e}
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You can install this by running;
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pip install git+https://github.com/litex-hub/litex-data-{dt}-{dn}.git
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""".format(dt=data_type, dn=data_name, e=e))
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@ -32,7 +32,7 @@ import os
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from migen import *
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from migen import *
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from litex.data.find import find_data
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from litex import get_data_mod
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from litex.soc.interconnect import axi
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from litex.soc.interconnect import axi
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.cpu import CPU
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from litex.soc.cores.cpu import CPU
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@ -116,7 +116,8 @@ class BlackParrotRV64(CPU):
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@staticmethod
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@staticmethod
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def add_sources(platform, variant="standard"):
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def add_sources(platform, variant="standard"):
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filename = os.path.join(find_data("cpu", "blackparrot"), "flist_litex.verilator")
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filename = get_data_mod("cpu", "blackparrot").data_file(
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"flist_litex.verilator")
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with open(filename) as openfileobject:
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with open(filename) as openfileobject:
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for line in openfileobject:
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for line in openfileobject:
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temp = line
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temp = line
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@ -9,7 +9,7 @@ import os
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from migen import *
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from migen import *
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from litex.data.find import find_data
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from litex import get_data_mod
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.cpu import CPU
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from litex.soc.cores.cpu import CPU
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@ -97,7 +97,7 @@ class LM32(CPU):
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@staticmethod
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@staticmethod
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def add_sources(platform, variant):
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def add_sources(platform, variant):
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vdir = find_data("cpu", "lm32")
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vdir = get_data_mod("cpu", "lm32").data_location
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platform.add_sources(os.path.join(vdir, "rtl"),
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platform.add_sources(os.path.join(vdir, "rtl"),
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"lm32_cpu.v",
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"lm32_cpu.v",
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"lm32_instruction_unit.v",
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"lm32_instruction_unit.v",
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@ -6,7 +6,7 @@ import os
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from migen import *
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from migen import *
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from litex.data.find import find_data
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from litex import get_data_mod
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.cpu import CPU
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from litex.soc.cores.cpu import CPU
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@ -99,7 +99,9 @@ class Microwatt(CPU):
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@staticmethod
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@staticmethod
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def add_sources(platform):
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def add_sources(platform):
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sdir = os.path.join(find_data("cpu", "microwatt"), "sources")
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sdir = os.path.join(
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get_data_mod("cpu", "microwatt").data_location,
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"sources")
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platform.add_sources(sdir,
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platform.add_sources(sdir,
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# Common / Types / Helpers
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# Common / Types / Helpers
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"decode_types.vhdl",
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"decode_types.vhdl",
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@ -8,7 +8,7 @@ import os
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from migen import *
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from migen import *
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from litex.data.find import find_data
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from litex import get_data_mod
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.cpu import CPU
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from litex.soc.cores.cpu import CPU
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@ -174,7 +174,8 @@ class MOR1KX(CPU):
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@staticmethod
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@staticmethod
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def add_sources(platform):
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def add_sources(platform):
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vdir = os.path.join(
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vdir = os.path.join(
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find_data("cpu", "mor1kx"), "rtl", "verilog")
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get_data_mod("cpu", "mor1kx").data_location,
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"rtl", "verilog")
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platform.add_source_dir(vdir)
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platform.add_source_dir(vdir)
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platform.add_verilog_include_path(vdir)
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platform.add_verilog_include_path(vdir)
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@ -11,7 +11,7 @@ import os
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from migen import *
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from migen import *
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from litex.data.find import find_data
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from litex import get_data_mod
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.cpu import CPU
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from litex.soc.cores.cpu import CPU
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@ -180,7 +180,7 @@ class PicoRV32(CPU):
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@staticmethod
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@staticmethod
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def add_sources(platform):
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def add_sources(platform):
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vdir = find_data("cpu", "picorv32")
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vdir = get_data_mod("cpu", "picorv32").data_location
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platform.add_source(os.path.join(vdir, "picorv32.v"))
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platform.add_source(os.path.join(vdir, "picorv32.v"))
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def do_finalize(self):
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def do_finalize(self):
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@ -33,7 +33,7 @@ import os
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from migen import *
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from migen import *
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from litex.data.find import find_data
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from litex import get_data_mod
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from litex.soc.interconnect import axi
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from litex.soc.interconnect import axi
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.cpu import CPU
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from litex.soc.cores.cpu import CPU
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@ -239,7 +239,7 @@ class RocketRV64(CPU):
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@staticmethod
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@staticmethod
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def add_sources(platform, variant="standard"):
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def add_sources(platform, variant="standard"):
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vdir = find_data("cpu", "rocket")
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vdir = get_data_mod("cpu", "rocket").data_location
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platform.add_sources(
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platform.add_sources(
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os.path.join(vdir, "generated-src"),
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os.path.join(vdir, "generated-src"),
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CPU_VARIANTS[variant] + ".v",
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CPU_VARIANTS[variant] + ".v",
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@ -12,7 +12,7 @@ import os
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from migen import *
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from migen import *
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from litex.data.find import find_data
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from litex import get_data_mod
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect.csr import *
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from litex.soc.interconnect.csr import *
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from litex.soc.cores.cpu import CPU
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from litex.soc.cores.cpu import CPU
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@ -247,7 +247,7 @@ class VexRiscv(CPU, AutoCSR):
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@staticmethod
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@staticmethod
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def add_sources(platform, variant="standard"):
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def add_sources(platform, variant="standard"):
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cpu_filename = CPU_VARIANTS[variant] + ".v"
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cpu_filename = CPU_VARIANTS[variant] + ".v"
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vdir = find_data("cpu", "vexriscv")
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vdir = get_data_mod("cpu", "vexriscv").data_location
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platform.add_source(os.path.join(vdir, cpu_filename))
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platform.add_source(os.path.join(vdir, cpu_filename))
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def use_external_variant(self, variant_filename):
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def use_external_variant(self, variant_filename):
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import struct
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import struct
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import shutil
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import shutil
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from litex import get_data_mod
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from litex.build.tools import write_to_file
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from litex.build.tools import write_to_file
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from litex.data.find import find_data
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from litex.soc.integration import export, soc_core
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from litex.soc.integration import export, soc_core
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__all__ = ["soc_software_packages", "soc_directory",
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__all__ = ["soc_software_packages", "soc_directory",
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for k, v in exec_profiles.items():
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for k, v in exec_profiles.items():
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define(k, v)
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define(k, v)
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define(
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define(
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"COMPILER_RT_DIRECTORY", find_data("software", "compiler_rt"))
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"COMPILER_RT_DIRECTORY",
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get_data_mod("software", "compiler_rt").data_location)
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define("SOC_DIRECTORY", soc_directory)
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define("SOC_DIRECTORY", soc_directory)
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variables_contents.append("export BUILDINC_DIRECTORY\n")
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variables_contents.append("export BUILDINC_DIRECTORY\n")
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define("BUILDINC_DIRECTORY", self.include_dir)
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define("BUILDINC_DIRECTORY", self.include_dir)
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("migen", ("https://github.com/m-labs/", True, True)),
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("migen", ("https://github.com/m-labs/", True, True)),
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# LiteX SoC builder
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# LiteX SoC builder
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('litex-data-software-compiler_rt', ("https://github.com/litex-hub/", False, True)),
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("pythondata-software-compiler_rt", ("https://github.com/litex-hub/", False, True)),
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("litex", ("https://github.com/enjoy-digital/", False, True)),
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("litex", ("https://github.com/enjoy-digital/", False, True)),
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# LiteX cores ecosystem
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# LiteX cores ecosystem
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("litex-boards", ("https://github.com/litex-hub/", False, True)),
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("litex-boards", ("https://github.com/litex-hub/", False, True)),
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# Optional LiteX data
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# Optional LiteX data
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("litex-data-cpu-blackparrot", ("https://github.com/litex-hub/", False, True)),
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("pythondata-cpu-blackparrot", ("https://github.com/litex-hub/", False, True)),
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("litex-data-cpu-mor1kx", ("https://github.com/litex-hub/", False, True)),
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("pythondata-cpu-mor1kx", ("https://github.com/litex-hub/", False, True)),
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("litex-data-cpu-lm32", ("https://github.com/litex-hub/", False, True)),
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("pythondata-cpu-lm32", ("https://github.com/litex-hub/", False, True)),
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("litex-data-cpu-microwatt", ("https://github.com/litex-hub/", False, True)),
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("pythondata-cpu-microwatt", ("https://github.com/litex-hub/", False, True)),
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("litex-data-cpu-picorv32", ("https://github.com/litex-hub/", False, True)),
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("pythondata-cpu-picorv32", ("https://github.com/litex-hub/", False, True)),
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("litex-data-cpu-rocket", ("https://github.com/litex-hub/", False, True)),
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("pythondata-cpu-rocket", ("https://github.com/litex-hub/", False, True)),
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("litex-data-cpu-vexriscv", ("https://github.com/litex-hub/", False, True)),
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("pythondata-cpu-vexriscv", ("https://github.com/litex-hub/", False, True)),
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("litex-data-misc-tapcfg", ("https://github.com/litex-hub/", False, True)),
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("pythondata-misc-tapcfg", ("https://github.com/litex-hub/", False, True)),
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]
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]
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repos = OrderedDict(repos)
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repos = OrderedDict(repos)
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2
setup.py
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setup.py
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install_requires=[
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install_requires=[
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"migen",
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"migen",
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"pyserial",
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"pyserial",
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"litex-data-software-compiler_rt",
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"pythondata-software-compiler_rt",
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],
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],
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packages=find_packages(exclude=("test*", "sim*", "doc*")),
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packages=find_packages(exclude=("test*", "sim*", "doc*")),
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include_package_data=True,
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include_package_data=True,
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