Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

cores/ram/lattice_nx: Revert #1906 since not working with RAM combining multiple SP512K.

This commit is contained in:
Florent Kermarrec 2024-07-22 14:24:34 +02:00
parent 4662b95f16
commit ecd0f0e548
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
litex/soc/cores/ram/lattice_nx.py
View File

@ -79,10 +79,10 @@ class NXLRAM(LiteXModule):
wren = Signal()
self.comb += [
datain.eq(self.bus.dat_w[32*w:32*(w+1)]),
self.bus.dat_r[32*w:32*(w+1)].eq(dataout),
If(self.bus.adr[14:14+self.depth_cascading.bit_length()] == d,
cs.eq(1),
wren.eq(self.bus.we & self.bus.stb & self.bus.cyc)
wren.eq(self.bus.we & self.bus.stb & self.bus.cyc),
self.bus.dat_r[32*w:32*(w+1)].eq(dataout),
),
]
lram_block = Instance("SP512K",