Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

cpu/vexriscv/core: Rename timer_enabled parameter to with_timer (for consistency with codebase) and disable timer by default (since increasing resources and causing issue on some iCE40 designs).

Browse source
This commit is contained in:
Florent Kermarrec 2021-03-09 09:07:32 +01:00
parent 834c90b71f
commit ece9005949
1 changed files with 2 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
litex/soc/cores/cpu/vexriscv/core.py
View file

@ -111,7 +111,7 @@ class VexRiscv(CPU, AutoCSR):
flags += " -D__vexriscv__"
return flags
def __init__(self, platform, variant="standard", timer_enabled=True):
def __init__(self, platform, variant="standard", with_timer=False):
self.platform = platform
self.variant = variant
self.human_name = CPU_VARIANTS.get(variant, "VexRiscv")
@ -158,7 +158,7 @@ class VexRiscv(CPU, AutoCSR):
i_dBusWishbone_ERR = dbus.err
)
if timer_enabled:
if with_timer:
self.add_timer()
if "debug" in variant: