litex/gen: Add some comments.

This commit is contained in:
Florent Kermarrec 2023-07-27 16:18:30 +02:00
parent 095cfb7811
commit ed12f8787d
3 changed files with 31 additions and 4 deletions

View file

@ -6,9 +6,10 @@
from migen import * from migen import *
# Generic Helpers ---------------------------------------------------------------------------------- # Coloring Helpers ---------------------------------------------------------------------------------
def colorer(s, color="bright"): def colorer(s, color="bright"):
"""Apply ANSI colors to a string."""
header = { header = {
"bright": "\x1b[1m", "bright": "\x1b[1m",
"green": "\x1b[32m", "green": "\x1b[32m",
@ -22,9 +23,11 @@ def colorer(s, color="bright"):
# Bit/Bytes Reversing ------------------------------------------------------------------------------ # Bit/Bytes Reversing ------------------------------------------------------------------------------
def reverse_bits(s): def reverse_bits(s):
"""Return a signal with reversed bit order."""
return s[::-1] return s[::-1]
def reverse_bytes(s): def reverse_bytes(s):
"""Return a signal with reversed byte order."""
n = (len(s) + 7)//8 n = (len(s) + 7)//8
return Cat(*[s[i*8:min((i + 1)*8, len(s))] return Cat(*[s[i*8:min((i + 1)*8, len(s))]
for i in reversed(range(n))]) for i in reversed(range(n))])

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@ -8,9 +8,19 @@ from migen import *
# LiteX Context ------------------------------------------------------------------------------------ # LiteX Context ------------------------------------------------------------------------------------
# FIXME: PoC to fix Efinix AsyncFIFO issue, think a bit more about it to see how to do it properly.
class LiteXContext: class LiteXContext:
"""
A context for LiteX-related settings.
This class serves as a container for the platform, toolchain, device,
and system-on-a-chip (SoC) information for a given LiteX project.
Attributes:
platform : The FPGA Platform of the project.
toolchain : The FPGA Toolchain to be used for synthesis and place-and-route.
device : The FPGA Device of the LiteX project.
soc : The FPGA SoC of the LiteX project.
"""
platform = None platform = None
toolchain = None toolchain = None
device = None device = None

View file

@ -8,14 +8,28 @@ from migen import *
# Signals ------------------------------------------------------------------------------------------ # Signals ------------------------------------------------------------------------------------------
class Open(Signal): pass class Open(Signal):
"""A base Signal class, representing an open signal."""
pass
class Unsigned(Signal): class Unsigned(Signal):
"""
A Signal subclass for unsigned signals.
Args:
bits (int): Number of bits of the signal. Defaults to 1.
"""
def __init__(self, bits=1, *args, **kwargs): def __init__(self, bits=1, *args, **kwargs):
assert isinstance(bits, int) assert isinstance(bits, int)
Signal.__init__(self, bits_sign=(bits, 0), *args, **kwargs) Signal.__init__(self, bits_sign=(bits, 0), *args, **kwargs)
class Signed(Signal): class Signed(Signal):
"""
A Signal subclass for signed signals.
Args:
bits (int): Number of bits of the signal. Defaults to 1.
"""
def __init__(self, bits=1, *args, **kwargs): def __init__(self, bits=1, *args, **kwargs):
assert isinstance(bits, int) assert isinstance(bits, int)
Signal.__init__(self, bits_sign=(bits, 1), *args, **kwargs) Signal.__init__(self, bits_sign=(bits, 1), *args, **kwargs)