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litex/gen: Add some comments.
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3 changed files with 31 additions and 4 deletions
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@ -6,9 +6,10 @@
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from migen import *
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from migen import *
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# Generic Helpers ----------------------------------------------------------------------------------
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# Coloring Helpers ---------------------------------------------------------------------------------
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def colorer(s, color="bright"):
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def colorer(s, color="bright"):
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"""Apply ANSI colors to a string."""
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header = {
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header = {
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"bright": "\x1b[1m",
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"bright": "\x1b[1m",
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"green": "\x1b[32m",
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"green": "\x1b[32m",
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@ -22,9 +23,11 @@ def colorer(s, color="bright"):
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# Bit/Bytes Reversing ------------------------------------------------------------------------------
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# Bit/Bytes Reversing ------------------------------------------------------------------------------
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def reverse_bits(s):
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def reverse_bits(s):
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"""Return a signal with reversed bit order."""
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return s[::-1]
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return s[::-1]
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def reverse_bytes(s):
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def reverse_bytes(s):
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"""Return a signal with reversed byte order."""
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n = (len(s) + 7)//8
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n = (len(s) + 7)//8
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return Cat(*[s[i*8:min((i + 1)*8, len(s))]
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return Cat(*[s[i*8:min((i + 1)*8, len(s))]
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for i in reversed(range(n))])
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for i in reversed(range(n))])
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@ -8,9 +8,19 @@ from migen import *
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# LiteX Context ------------------------------------------------------------------------------------
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# LiteX Context ------------------------------------------------------------------------------------
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# FIXME: PoC to fix Efinix AsyncFIFO issue, think a bit more about it to see how to do it properly.
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class LiteXContext:
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class LiteXContext:
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"""
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A context for LiteX-related settings.
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This class serves as a container for the platform, toolchain, device,
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and system-on-a-chip (SoC) information for a given LiteX project.
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Attributes:
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platform : The FPGA Platform of the project.
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toolchain : The FPGA Toolchain to be used for synthesis and place-and-route.
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device : The FPGA Device of the LiteX project.
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soc : The FPGA SoC of the LiteX project.
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"""
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platform = None
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platform = None
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toolchain = None
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toolchain = None
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device = None
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device = None
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@ -8,14 +8,28 @@ from migen import *
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# Signals ------------------------------------------------------------------------------------------
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# Signals ------------------------------------------------------------------------------------------
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class Open(Signal): pass
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class Open(Signal):
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"""A base Signal class, representing an open signal."""
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pass
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class Unsigned(Signal):
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class Unsigned(Signal):
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"""
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A Signal subclass for unsigned signals.
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Args:
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bits (int): Number of bits of the signal. Defaults to 1.
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"""
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def __init__(self, bits=1, *args, **kwargs):
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def __init__(self, bits=1, *args, **kwargs):
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assert isinstance(bits, int)
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assert isinstance(bits, int)
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Signal.__init__(self, bits_sign=(bits, 0), *args, **kwargs)
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Signal.__init__(self, bits_sign=(bits, 0), *args, **kwargs)
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class Signed(Signal):
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class Signed(Signal):
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"""
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A Signal subclass for signed signals.
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Args:
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bits (int): Number of bits of the signal. Defaults to 1.
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"""
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def __init__(self, bits=1, *args, **kwargs):
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def __init__(self, bits=1, *args, **kwargs):
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assert isinstance(bits, int)
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assert isinstance(bits, int)
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Signal.__init__(self, bits_sign=(bits, 1), *args, **kwargs)
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Signal.__init__(self, bits_sign=(bits, 1), *args, **kwargs)
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