litex/gen: Split common in common/context/reduce/signal.

This commit is contained in:
Florent Kermarrec 2023-07-27 15:02:37 +02:00
parent 74401d6f03
commit 095cfb7811
5 changed files with 76 additions and 51 deletions

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@ -1,3 +1,8 @@
from litex.gen.sim import *
from litex.gen.common import *
from litex.gen.signal import *
from litex.gen.reduce import *
from litex.gen.context import *
from litex.gen.fhdl.module import *

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@ -24,58 +24,7 @@ def colorer(s, color="bright"):
def reverse_bits(s):
return s[::-1]
def reverse_bytes(s):
n = (len(s) + 7)//8
return Cat(*[s[i*8:min((i + 1)*8, len(s))]
for i in reversed(range(n))])
# Context ------------------------------------------------------------------------------------------
# FIXME: PoC to fix Efinix AsyncFIFO issue, think a bit more about it to see how to do it properly.
class LiteXContext:
platform = None
toolchain = None
device = None
soc = None
# Signals ------------------------------------------------------------------------------------------
class Open(Signal): pass
class Unsigned(Signal):
def __init__(self, bits=1, *args, **kwargs):
assert isinstance(bits, int)
Signal.__init__(self, bits_sign=(bits, 0), *args, **kwargs)
class Signed(Signal):
def __init__(self, bits=1, *args, **kwargs):
assert isinstance(bits, int)
Signal.__init__(self, bits_sign=(bits, 1), *args, **kwargs)
# Reduction ----------------------------------------------------------------------------------------
from functools import reduce
from operator import and_, or_, not_, xor, add
def Reduce(operator, value):
# List of supported Operators.
operators = {
"AND" : and_,
"OR" : or_,
"NOR" : not_,
"XOR" : xor,
"ADD" : add,
}
# Switch to upper-case.
operator = operator.upper()
# Check if provided operator is supported.
if operator not in operators.keys():
supported = ", ".join(operators.keys())
raise ValueError(f"Reduce does not support {operator} operator; supported: {supported}.")
# Return Python's reduction.
return reduce(operators[operator], value)

17
litex/gen/context.py Normal file
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@ -0,0 +1,17 @@
#
# This file is part of LiteX.
#
# This file is Copyright (c) 2023 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
# LiteX Context ------------------------------------------------------------------------------------
# FIXME: PoC to fix Efinix AsyncFIFO issue, think a bit more about it to see how to do it properly.
class LiteXContext:
platform = None
toolchain = None
device = None
soc = None

33
litex/gen/reduce.py Normal file
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@ -0,0 +1,33 @@
#
# This file is part of LiteX.
#
# This file is Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from functools import reduce
from operator import and_, or_, not_, xor, add
# Reduction ----------------------------------------------------------------------------------------
def Reduce(operator, value):
# List of supported Operators.
operators = {
"AND" : and_,
"OR" : or_,
"NOR" : not_,
"XOR" : xor,
"ADD" : add,
}
# Switch to upper-case.
operator = operator.upper()
# Check if provided operator is supported.
if operator not in operators.keys():
supported = ", ".join(operators.keys())
raise ValueError(f"Reduce does not support {operator} operator; supported: {supported}.")
# Return Python's reduction.
return reduce(operators[operator], value)

21
litex/gen/signal.py Normal file
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@ -0,0 +1,21 @@
#
# This file is part of LiteX.
#
# This file is Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
# Signals ------------------------------------------------------------------------------------------
class Open(Signal): pass
class Unsigned(Signal):
def __init__(self, bits=1, *args, **kwargs):
assert isinstance(bits, int)
Signal.__init__(self, bits_sign=(bits, 0), *args, **kwargs)
class Signed(Signal):
def __init__(self, bits=1, *args, **kwargs):
assert isinstance(bits, int)
Signal.__init__(self, bits_sign=(bits, 1), *args, **kwargs)