test: add test_axi_lite (with test code from soc/interconnect/axi_lite lightly modified)
This commit is contained in:
Florent Kermarrec
parent
4aa07f2ae9
commit
ed2578799b
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@ -178,101 +178,3 @@ class AXILite2CSR(Module):
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NextState('IDLE'),
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)
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)
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from migen.sim import run_simulation
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from litex.soc.interconnect import csr, csr_bus
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def test_axilite2csr():
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class CSRHolder(Module, csr.AutoCSR):
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def __init__(self):
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self.foo = csr.CSRStorage(32, reset=1)
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self.bar = csr.CSRStorage(32, reset=1)
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class Fixture(Module):
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def __init__(self):
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self.csr = csr_bus.Interface(data_width=32, address_width=12)
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self.axi = Interface(data_width=32, address_width=14)
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self.submodules.holder = CSRHolder()
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self.submodules.dut = AXILite2CSR(self.axi, self.csr)
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self.submodules.csrbankarray = csr_bus.CSRBankArray(
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self, self.map_csr, data_width=32, address_width=12)
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self.submodules.csrcon = csr_bus.Interconnect(
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self.csr, self.csrbankarray.get_buses())
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def map_csr(self, name, memory):
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return {
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'holder': 0,
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}[name]
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def testbench_write_read(dut):
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axi = dut.axi
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for _ in range(8):
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yield
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# Write test
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yield axi.aw.valid.eq(1)
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yield axi.aw.addr.eq(4)
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yield axi.w.valid.eq(1)
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yield axi.b.ready.eq(1)
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yield axi.w.data.eq(0x2137)
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while (yield axi.aw.ready) != 1:
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yield
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while (yield axi.w.ready) != 1:
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yield
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yield axi.aw.valid.eq(0)
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yield axi.w.valid.eq(0)
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for _ in range(8):
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yield
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# Read test
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yield axi.ar.valid.eq(1)
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yield axi.r.ready.eq(1)
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yield axi.ar.addr.eq(4)
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while (yield axi.ar.ready != 1):
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yield
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yield axi.ar.valid.eq(0)
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while (yield axi.r.valid != 1):
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yield
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yield axi.r.ready.eq(0)
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read = yield axi.r.data
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assert read == 0x2137
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for _ in range(8):
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yield
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def testbench_simultaneous(dut):
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axi = dut.axi
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for _ in range(8):
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yield
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# Write
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yield axi.aw.valid.eq(1)
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yield axi.aw.addr.eq(2)
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yield axi.w.valid.eq(1)
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yield axi.b.ready.eq(1)
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yield axi.w.data.eq(0x2137)
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# Read
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yield axi.ar.valid.eq(1)
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yield axi.r.ready.eq(1)
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yield axi.ar.addr.eq(2)
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yield
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yield
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is_reading = yield axi.ar.ready
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is_writing = yield axi.aw.ready
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assert is_reading
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assert not is_writing
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fixture = Fixture()
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run_simulation(fixture, testbench_write_read(fixture.dut), vcd_name='axi-write-read.vcd')
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fixture = Fixture()
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run_simulation(fixture, testbench_simultaneous(fixture.dut), vcd_name='axi-simultaneous.vcd')
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@ -0,0 +1,104 @@
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import unittest
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from migen import *
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from litex.soc.interconnect import csr
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from litex.soc.interconnect import csr_bus
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from litex.soc.interconnect import axi_lite
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class CSRModule(Module, csr.AutoCSR):
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def __init__(self):
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self.foo = csr.CSRStorage(32, reset=1)
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self.bar = csr.CSRStorage(32, reset=1)
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class AXILiteDUT(Module):
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def __init__(self):
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self.csr = csr_bus.Interface(data_width=32, address_width=12)
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self.axi = axi_lite.Interface(data_width=32, address_width=14)
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self.submodules.csrmodule = CSRModule()
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self.submodules.dut = axi_lite.AXILite2CSR(self.axi, self.csr)
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self.submodules.csrbankarray = csr_bus.CSRBankArray(
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self, self.map_csr, data_width=32, address_width=12)
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self.submodules.csrcon = csr_bus.Interconnect(
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self.csr, self.csrbankarray.get_buses())
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def map_csr(self, name, memory):
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return {"csrmodule": 0}[name]
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class TestAXILite(unittest.TestCase):
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def test_write_read(self):
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def generator(dut):
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axi = dut.axi
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for _ in range(8):
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yield
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# Write test
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yield axi.aw.valid.eq(1)
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yield axi.aw.addr.eq(4)
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yield axi.w.valid.eq(1)
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yield axi.b.ready.eq(1)
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yield axi.w.data.eq(0x2137)
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while (yield axi.aw.ready) != 1:
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yield
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while (yield axi.w.ready) != 1:
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yield
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yield axi.aw.valid.eq(0)
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yield axi.w.valid.eq(0)
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for _ in range(8):
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yield
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# Read test
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yield axi.ar.valid.eq(1)
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yield axi.r.ready.eq(1)
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yield axi.ar.addr.eq(4)
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while (yield axi.ar.ready != 1):
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yield
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yield axi.ar.valid.eq(0)
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while (yield axi.r.valid != 1):
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yield
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yield axi.r.ready.eq(0)
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read = yield axi.r.data
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assert read == 0x2137
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for _ in range(8):
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yield
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dut = AXILiteDUT()
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run_simulation(dut, generator(dut.dut), vcd_name='axi-write-read.vcd')
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def test_simultaneous(dut):
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def generator(dut):
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axi = dut.axi
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for _ in range(8):
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yield
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# Write
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yield axi.aw.valid.eq(1)
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yield axi.aw.addr.eq(2)
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yield axi.w.valid.eq(1)
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yield axi.b.ready.eq(1)
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yield axi.w.data.eq(0x2137)
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# Read
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yield axi.ar.valid.eq(1)
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yield axi.r.ready.eq(1)
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yield axi.ar.addr.eq(2)
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yield
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yield
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is_reading = yield axi.ar.ready
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is_writing = yield axi.aw.ready
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assert is_reading
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assert not is_writing
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dut = AXILiteDUT()
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run_simulation(dut, generator(dut.dut), vcd_name='axi-simultaneous.vcd')
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