soc/cores/bitbang: fix missing self.comb on miso.
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@ -86,5 +86,5 @@ class SPIMaster(Module, AutoCSR):
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self._r.fields.mosi.eq(_mosi_r),
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self._r.fields.mosi.eq(_mosi_r),
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]
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]
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if hasattr(pads, "miso"):
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if hasattr(pads, "miso"):
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self._r.fields.miso.eq(pads.miso)
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self.comb += self._r.fields.miso.eq(pads.miso)
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self.specials += Tristate(pads.mosi, _mosi_w, _mosi_oe, _mosi_r)
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self.specials += Tristate(pads.mosi, _mosi_w, _mosi_oe, _mosi_r)
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