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AvalonMM2Wishbone: fix burst reads (#1686)

This commit is contained in:
Hans Baier 2023-05-10 05:22:23 +07:00
parent 71a0e398a7
commit ef904a14e1
1 changed files with 4 additions and 1 deletions
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5
litex/soc/interconnect/avalon/avalon_mm_to_wishbone.py
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@ -59,7 +59,6 @@ class AvalonMM2Wishbone(Module):
self.comb += [ self.comb += [
avl.waitrequest.eq(~(wb.ack | wb.err) | burst_read), avl.waitrequest.eq(~(wb.ack | wb.err) | burst_read),
avl.readdata.eq(readdata), avl.readdata.eq(readdata),
avl.readdatavalid.eq(readdatavalid),
] ]
# Avalon -> Wishbone # Avalon -> Wishbone
@ -79,6 +78,7 @@ class AvalonMM2Wishbone(Module):
self.submodules.fsm = fsm = FSM(reset_state="SINGLE") self.submodules.fsm = fsm = FSM(reset_state="SINGLE")
fsm.act("SINGLE", fsm.act("SINGLE",
burst_cycle.eq(0), burst_cycle.eq(0),
avl.readdatavalid.eq(readdatavalid),
wb.sel.eq(avl.byteenable), wb.sel.eq(avl.byteenable),
wb.cti.eq(wishbone.CTI_BURST_NONE), wb.cti.eq(wishbone.CTI_BURST_NONE),
If(avl.burstcount > 1, If(avl.burstcount > 1,
@ -97,6 +97,7 @@ class AvalonMM2Wishbone(Module):
) )
) )
fsm.act("BURST-WRITE", fsm.act("BURST-WRITE",
avl.readdatavalid.eq(0),
burst_cycle.eq(1), burst_cycle.eq(1),
wb.sel.eq(avl.byteenable), wb.sel.eq(avl.byteenable),
wb.cti.eq(wishbone.CTI_BURST_INCREMENTING), wb.cti.eq(wishbone.CTI_BURST_INCREMENTING),
@ -113,6 +114,7 @@ class AvalonMM2Wishbone(Module):
) )
) )
fsm.act("BURST-READ", fsm.act("BURST-READ",
avl.readdatavalid.eq(0),
burst_cycle.eq(1), burst_cycle.eq(1),
burst_read.eq(1), burst_read.eq(1),
wb.stb.eq(1), wb.stb.eq(1),
@ -122,6 +124,7 @@ class AvalonMM2Wishbone(Module):
wb.cti.eq(wishbone.CTI_BURST_END) wb.cti.eq(wishbone.CTI_BURST_END)
), ),
If(wb.ack, If(wb.ack,
avl.readdatavalid.eq(1),
NextValue(burst_address, burst_address + word_width), NextValue(burst_address, burst_address + word_width),
NextValue(burst_count, burst_count - 1) NextValue(burst_count, burst_count - 1)
), ),