Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

tools/litex_sim: add cli options to control SDRAM timing checker

This commit is contained in:
Piotr Binkowski 2020-02-13 14:45:15 +01:00
parent e4712ff7f3
commit eff85a99bb
1 changed files with 27 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
litex/tools/litex_sim.py
View File

@ -160,6 +160,8 @@ class SimSoC(SoCSDRAM):
sdram_module = "MT48LC16M16",
sdram_init = [],
sdram_data_width = 32,
sdram_timing_checker = False,
sdram_verbose_timings = False,
**kwargs):
platform = Platform()
sys_clk_freq = int(1e6)
@ -189,7 +191,13 @@ class SimSoC(SoCSDRAM):
memtype = sdram_module.memtype,
data_width = sdram_data_width,
clk_freq = sdram_clk_freq)
self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings, init=sdram_init)
self.submodules.sdrphy = SDRAMPHYModel(
sdram_module,
phy_settings,
sdram_clk_freq,
use_timing_checker=sdram_timing_checker,
verbose_timing_checker=sdram_verbose_timings,
init=sdram_init)
self.register_sdram(
self.sdrphy,
sdram_module.geom_settings,
@ -254,6 +262,8 @@ def main():
parser.add_argument("--sdram-module", default="MT48LC16M16", help="Select SDRAM chip")
parser.add_argument("--sdram-data-width", default=32, help="Set SDRAM chip data width")
parser.add_argument("--sdram-init", default=None, help="SDRAM init file")
parser.add_argument("--sdram-no-timing", action="store_true", help="Disable SDRAM timing verification checks")
parser.add_argument("--sdram-verbose-timing", action="store_true", help="Enable SDRAM verbose timing logging")
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
parser.add_argument("--with-analyzer", action="store_true", help="Enable Analyzer support")
@ -287,6 +297,8 @@ def main():
soc_kwargs["integrated_main_ram_size"] = 0x0
soc_kwargs["sdram_module"] = args.sdram_module
soc_kwargs["sdram_data_width"] = int(args.sdram_data_width)
soc_kwargs["sdram_timing_checker"] = not args.sdram_no_timing
soc_kwargs["sdram_verbose_timings"] = args.sdram_verbose_timing
if args.with_ethernet or args.with_etherbone:
sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": "192.168.1.100"})