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targets/sim: update sdram (manual cmd_latency no longer needed).

This commit is contained in:
Florent Kermarrec 2020-10-12 17:35:39 +02:00
parent bc68351475
commit f0abc185e1
4 changed files with 7 additions and 14 deletions
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3
litex/boards/targets/genesys2.py
View File

@ -63,8 +63,7 @@ class BaseSoC(SoCCore):
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
memtype = "DDR3", memtype = "DDR3",
nphases = 4, nphases = 4,
sys_clk_freq = sys_clk_freq, sys_clk_freq = sys_clk_freq)
cmd_latency = 1)
self.add_csr("ddrphy") self.add_csr("ddrphy")
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,

3
litex/boards/targets/kc705.py
View File

@ -65,8 +65,7 @@ class BaseSoC(SoCCore):
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
memtype = "DDR3", memtype = "DDR3",
nphases = 4, nphases = 4,
sys_clk_freq = sys_clk_freq, sys_clk_freq = sys_clk_freq)
cmd_latency = 1)
self.add_csr("ddrphy") self.add_csr("ddrphy")
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,

3
litex/boards/targets/kcu105.py
View File

@ -74,8 +74,7 @@ class BaseSoC(SoCCore):
self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"), self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"),
memtype = "DDR4", memtype = "DDR4",
sys_clk_freq = sys_clk_freq, sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 200e6, iodelay_clk_freq = 200e6)
cmd_latency = 1)
self.add_csr("ddrphy") self.add_csr("ddrphy")
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,

12
litex/tools/litex_sim.py
View File

@ -114,27 +114,23 @@ def get_sdram_phy_settings(memtype, data_width, clk_freq):
elif memtype in ["DDR2", "DDR3"]: elif memtype in ["DDR2", "DDR3"]:
# Settings from s7ddrphy # Settings from s7ddrphy
tck = 2/(2*nphases*clk_freq) tck = 2/(2*nphases*clk_freq)
cmd_latency = 0
cl, cwl = get_cl_cw(memtype, tck) cl, cwl = get_cl_cw(memtype, tck)
cl_sys_latency = get_sys_latency(nphases, cl) cl_sys_latency = get_sys_latency(nphases, cl)
cwl = cwl + cmd_latency
cwl_sys_latency = get_sys_latency(nphases, cwl) cwl_sys_latency = get_sys_latency(nphases, cwl)
rdphase = get_sys_phase(nphases, cl_sys_latency, cl) rdphase = get_sys_phase(nphases, cl_sys_latency, cl)
wrphase = get_sys_phase(nphases, cwl_sys_latency, cwl) wrphase = get_sys_phase(nphases, cwl_sys_latency, cwl)
read_latency = 2 + cl_sys_latency + 2 + 3 read_latency = cl_sys_latency + 6
write_latency = cwl_sys_latency write_latency = cwl_sys_latency - 1
elif memtype == "DDR4": elif memtype == "DDR4":
# Settings from usddrphy # Settings from usddrphy
tck = 2/(2*nphases*clk_freq) tck = 2/(2*nphases*clk_freq)
cmd_latency = 0
cl, cwl = get_cl_cw(memtype, tck) cl, cwl = get_cl_cw(memtype, tck)
cl_sys_latency = get_sys_latency(nphases, cl) cl_sys_latency = get_sys_latency(nphases, cl)
cwl = cwl + cmd_latency
cwl_sys_latency = get_sys_latency(nphases, cwl) cwl_sys_latency = get_sys_latency(nphases, cwl)
rdphase = get_sys_phase(nphases, cl_sys_latency, cl) rdphase = get_sys_phase(nphases, cl_sys_latency, cl)
wrphase = get_sys_phase(nphases, cwl_sys_latency, cwl) wrphase = get_sys_phase(nphases, cwl_sys_latency, cwl)
read_latency = 2 + cl_sys_latency + 1 + 3 read_latency = cl_sys_latency + 5
write_latency = cwl_sys_latency write_latency = cwl_sys_latency - 1
sdram_phy_settings = { sdram_phy_settings = {
"nphases": nphases, "nphases": nphases,