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tools/litex_sim: use default integrated_rom_size

This commit is contained in:
Florent Kermarrec 2020-01-13 17:39:23 +01:00
parent 4648db0c2a
commit f1606dbc72
1 changed files with 0 additions and 1 deletions
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litex/tools/litex_sim.py
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@ -107,7 +107,6 @@ class SimSoC(SoCSDRAM):
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size = 0x8000,
ident = "LiteX Simulation", ident_version=True,
with_uart = False,
**kwargs)