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stream/ClockDomainCrossing: Revert with_common_rst to False by default (Previous behavior). 

This seems to cause issues in simulation on some cores, this will first have to be fixed before
using it as default. Cores requiring it will set it to True explicitly for now.
This commit is contained in:
Florent Kermarrec 2022-04-05 19:53:00 +02:00
parent ed6a6a83a9
commit f224036138
1 changed files with 1 additions and 1 deletions
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litex/soc/interconnect/stream.py
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@ -242,7 +242,7 @@ class AsyncFIFO(_FIFOWrapper):
# ClockDomainCrossing ------------------------------------------------------------------------------ # ClockDomainCrossing ------------------------------------------------------------------------------
class ClockDomainCrossing(Module): class ClockDomainCrossing(Module):
def __init__(self, layout, cd_from="sys", cd_to="sys", depth=None, with_common_rst=True): def __init__(self, layout, cd_from="sys", cd_to="sys", depth=None, with_common_rst=False):
self.sink = Endpoint(layout) self.sink = Endpoint(layout)
self.source = Endpoint(layout) self.source = Endpoint(layout)