Merge pull request #1355 from cklarhorst/master

integration/soc Add accessible_region to add_memory_buses

litex/soc/cores/cpu/naxriscv/core.py

@@ -196,6 +196,7 @@ class NaxRiscv(CPU):
         md5_hash.update(str(NaxRiscv.xlen).encode('utf-8'))
         md5_hash.update(str(NaxRiscv.jtag_tap).encode('utf-8'))
         md5_hash.update(str(NaxRiscv.jtag_instruction).encode('utf-8'))
+        md5_hash.update(str(NaxRiscv.memory_regions).encode('utf-8'))
         for args in NaxRiscv.scala_args:
             md5_hash.update(args.encode('utf-8'))
         for file in NaxRiscv.scala_paths:
@@ -227,7 +228,7 @@ class NaxRiscv(CPU):
         ndir = os.path.join(vdir, "ext", "NaxRiscv")
         sdir = os.path.join(vdir, "ext", "SpinalHDL")
 
-        NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git"  , "main", "b13c0aad")
+        NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git"  , "main", "cb2a598a")
         NaxRiscv.git_setup("SpinalHDL", sdir, "https://github.com/SpinalHDL/SpinalHDL.git", "dev" , "a130f7b7")
 
         gen_args = []
@@ -235,6 +236,8 @@ class NaxRiscv(CPU):
         gen_args.append(f"--netlist-directory={vdir}")
         gen_args.append(f"--reset-vector={reset_address}")
         gen_args.append(f"--xlen={NaxRiscv.xlen}")
+        for region in NaxRiscv.memory_regions:
+            gen_args.append(f"--memory-region={region[0]},{region[1]},{region[2]},{region[3]}")
         for args in NaxRiscv.scala_args:
             gen_args.append(f"--scala-args={args}")
         if(NaxRiscv.jtag_tap) :
@@ -395,6 +398,7 @@ class NaxRiscv(CPU):
             o_peripheral_clint_rresp   = clintbus.r.resp,
         )
         soc.bus.add_slave("clint", clintbus, region=soc_region_cls(origin=soc.mem_map.get("clint"), size=0x1_0000, cached=False))
+        self.soc = soc # Save SoC instance to retrieve the final mem layout on finalization
 
     def add_memory_buses(self, address_width, data_width):
         nax_data_width = 64
@@ -463,8 +467,29 @@ class NaxRiscv(CPU):
 
     def do_finalize(self):
         assert hasattr(self, "reset_address")
-
         self.find_scala_files()
+
+        # Generate memory map from CPU perspective
+        # naxriscv modes:
+        # r,w,x,c  : readable, writeable, executable, caching allowed
+        # io       : IO region (Implies P bus, preserve memory order, no dcache)
+        # naxriscv bus:
+        # p        : peripheral
+        # m        : memory
+        NaxRiscv.memory_regions = []
+        for name, region in self.soc.bus.io_regions.items():
+            NaxRiscv.memory_regions.append( (region.origin, region.size, "io", "p") ) # IO is only allowed on the p bus
+        for name, region in self.soc.bus.regions.items():
+            if region.linker: # remove virtual regions
+                continue
+            if len(self.memory_buses) and name == 'main_ram': # m bus
+                bus = "m"
+            else:
+                bus = "p"
+            mode = region.mode
+            mode += "c" if region.cached else ""
+            NaxRiscv.memory_regions.append( (region.origin, region.size, mode, bus) )
+
         self.generate_netlist_name(self.reset_address)
 
         # Do verilog instance.

litex/soc/cores/cpu/vexriscv_smp/core.py

@@ -445,7 +445,7 @@ class VexRiscvSMP(CPU):
         )
         soc.bus.add_slave("clint", clintbus, region=soc_region_cls(origin=soc.mem_map.get("clint"), size=0x1_0000, cached=False))
 
-    def add_memory_buses(self, address_width, data_width):
+    def add_memory_buses(self, address_width, data_width, accessible_region):
         VexRiscvSMP.litedram_width = data_width
 
         from litedram.common import LiteDRAMNativePort

litex/soc/integration/soc.py

@@ -886,7 +886,7 @@ class SoC(Module):
             colorer("added", color="green")))
         setattr(self.submodules, name, SoCController(**kwargs))
 
-    def add_ram(self, name, origin, size, contents=[], mode="rw"):
+    def add_ram(self, name, origin, size, contents=[], mode="rwx"):
         ram_cls = {
             "wishbone": wishbone.SRAM,
             "axi-lite": axi.AXILiteSRAM,
@@ -898,7 +898,7 @@ class SoC(Module):
             "axi"     : axi.AXILiteInterface, # FIXME: Use AXI-Lite for now, create AXISRAM.
         }[self.bus.standard]
         ram_bus = interface_cls(data_width=self.bus.data_width, bursting=self.bus.bursting)
-        ram     = ram_cls(size, bus=ram_bus, init=contents, read_only=(mode == "r"), name=name)
+        ram     = ram_cls(size, bus=ram_bus, init=contents, read_only=("w" not in mode), name=name)
         self.bus.add_slave(name, ram.bus, SoCRegion(origin=origin, size=size, mode=mode))
         self.check_if_exists(name)
         self.logger.info("RAM {} {} {}.".format(
@@ -909,7 +909,7 @@ class SoC(Module):
         if contents != []:
             self.add_config(f"{name}_INIT", 1)
 
-    def add_rom(self, name, origin, size, contents=[], mode="r"):
+    def add_rom(self, name, origin, size, contents=[], mode="rx"):
         self.add_ram(name, origin, size, contents, mode=mode)
 
     def init_rom(self, name, contents=[], auto_size=True):
@@ -917,7 +917,7 @@ class SoC(Module):
             colorer(name),
             colorer(f"0x{4*len(contents):x}")))
         getattr(self, name).mem.init = contents
-        if auto_size and self.bus.regions[name].mode == "r":
+        if auto_size and "w" not in self.bus.regions[name].mode:
             self.logger.info("Auto-Resizing ROM {} from {} to {}.".format(
                 colorer(name),
                 colorer(f"0x{self.bus.regions[name].size:x}"),
@@ -1475,13 +1475,16 @@ class LiteXSoC(SoC):
             sdram_size = min(sdram_size, size)
 
         # Add SDRAM region.
-        self.bus.add_region("main_ram", SoCRegion(origin=self.mem_map.get("main_ram", origin), size=sdram_size))
+        main_ram_region = SoCRegion(origin=self.mem_map.get("main_ram", origin), 
+                                    size=sdram_size,
+                                    mode="rwx")
+        self.bus.add_region("main_ram", main_ram_region)
 
         # Add CPU's direct memory buses (if not already declared) ----------------------------------
         if hasattr(self.cpu, "add_memory_buses"):
             self.cpu.add_memory_buses(
-                address_width = 32,
+                address_width      = 32,
-                data_width    = sdram.crossbar.controller.data_width
+                data_width         = sdram.crossbar.controller.data_width
             )
 
         # Connect CPU's direct memory buses to LiteDRAM --------------------------------------------

litex/soc/integration/soc_core.py

@@ -78,7 +78,7 @@ class SoCCore(LiteXSoC):
 
         # ROM parameters
         integrated_rom_size      = 0,
-        integrated_rom_mode      = "r",
+        integrated_rom_mode      = "rx",
         integrated_rom_init      = [],
 
         # SRAM parameters