Merge pull request #1355 from cklarhorst/master
integration/soc Add accessible_region to add_memory_buses
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Dolu1990
GitHub
commit
f2a088bfcc
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@ -196,6 +196,7 @@ class NaxRiscv(CPU):
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md5_hash.update(str(NaxRiscv.xlen).encode('utf-8'))
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md5_hash.update(str(NaxRiscv.jtag_tap).encode('utf-8'))
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md5_hash.update(str(NaxRiscv.jtag_instruction).encode('utf-8'))
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md5_hash.update(str(NaxRiscv.memory_regions).encode('utf-8'))
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for args in NaxRiscv.scala_args:
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md5_hash.update(args.encode('utf-8'))
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for file in NaxRiscv.scala_paths:
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@ -227,7 +228,7 @@ class NaxRiscv(CPU):
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ndir = os.path.join(vdir, "ext", "NaxRiscv")
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sdir = os.path.join(vdir, "ext", "SpinalHDL")
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NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git" , "main", "b13c0aad")
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NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git" , "main", "cb2a598a")
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NaxRiscv.git_setup("SpinalHDL", sdir, "https://github.com/SpinalHDL/SpinalHDL.git", "dev" , "a130f7b7")
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gen_args = []
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@ -235,6 +236,8 @@ class NaxRiscv(CPU):
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gen_args.append(f"--netlist-directory={vdir}")
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gen_args.append(f"--reset-vector={reset_address}")
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gen_args.append(f"--xlen={NaxRiscv.xlen}")
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for region in NaxRiscv.memory_regions:
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gen_args.append(f"--memory-region={region[0]},{region[1]},{region[2]},{region[3]}")
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for args in NaxRiscv.scala_args:
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gen_args.append(f"--scala-args={args}")
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if(NaxRiscv.jtag_tap) :
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@ -395,6 +398,7 @@ class NaxRiscv(CPU):
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o_peripheral_clint_rresp = clintbus.r.resp,
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)
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soc.bus.add_slave("clint", clintbus, region=soc_region_cls(origin=soc.mem_map.get("clint"), size=0x1_0000, cached=False))
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self.soc = soc # Save SoC instance to retrieve the final mem layout on finalization
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def add_memory_buses(self, address_width, data_width):
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nax_data_width = 64
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@ -463,8 +467,29 @@ class NaxRiscv(CPU):
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def do_finalize(self):
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assert hasattr(self, "reset_address")
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self.find_scala_files()
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# Generate memory map from CPU perspective
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# naxriscv modes:
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# r,w,x,c : readable, writeable, executable, caching allowed
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# io : IO region (Implies P bus, preserve memory order, no dcache)
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# naxriscv bus:
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# p : peripheral
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# m : memory
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NaxRiscv.memory_regions = []
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for name, region in self.soc.bus.io_regions.items():
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NaxRiscv.memory_regions.append( (region.origin, region.size, "io", "p") ) # IO is only allowed on the p bus
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for name, region in self.soc.bus.regions.items():
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if region.linker: # remove virtual regions
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continue
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if len(self.memory_buses) and name == 'main_ram': # m bus
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bus = "m"
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else:
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bus = "p"
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mode = region.mode
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mode += "c" if region.cached else ""
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NaxRiscv.memory_regions.append( (region.origin, region.size, mode, bus) )
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self.generate_netlist_name(self.reset_address)
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# Do verilog instance.
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@ -445,7 +445,7 @@ class VexRiscvSMP(CPU):
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)
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soc.bus.add_slave("clint", clintbus, region=soc_region_cls(origin=soc.mem_map.get("clint"), size=0x1_0000, cached=False))
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def add_memory_buses(self, address_width, data_width):
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def add_memory_buses(self, address_width, data_width, accessible_region):
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VexRiscvSMP.litedram_width = data_width
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from litedram.common import LiteDRAMNativePort
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@ -886,7 +886,7 @@ class SoC(Module):
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colorer("added", color="green")))
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setattr(self.submodules, name, SoCController(**kwargs))
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def add_ram(self, name, origin, size, contents=[], mode="rw"):
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def add_ram(self, name, origin, size, contents=[], mode="rwx"):
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ram_cls = {
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"wishbone": wishbone.SRAM,
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"axi-lite": axi.AXILiteSRAM,
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@ -898,7 +898,7 @@ class SoC(Module):
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"axi" : axi.AXILiteInterface, # FIXME: Use AXI-Lite for now, create AXISRAM.
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}[self.bus.standard]
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ram_bus = interface_cls(data_width=self.bus.data_width, bursting=self.bus.bursting)
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ram = ram_cls(size, bus=ram_bus, init=contents, read_only=(mode == "r"), name=name)
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ram = ram_cls(size, bus=ram_bus, init=contents, read_only=("w" not in mode), name=name)
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self.bus.add_slave(name, ram.bus, SoCRegion(origin=origin, size=size, mode=mode))
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self.check_if_exists(name)
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self.logger.info("RAM {} {} {}.".format(
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@ -909,7 +909,7 @@ class SoC(Module):
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if contents != []:
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self.add_config(f"{name}_INIT", 1)
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def add_rom(self, name, origin, size, contents=[], mode="r"):
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def add_rom(self, name, origin, size, contents=[], mode="rx"):
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self.add_ram(name, origin, size, contents, mode=mode)
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def init_rom(self, name, contents=[], auto_size=True):
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@ -917,7 +917,7 @@ class SoC(Module):
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colorer(name),
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colorer(f"0x{4*len(contents):x}")))
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getattr(self, name).mem.init = contents
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if auto_size and self.bus.regions[name].mode == "r":
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if auto_size and "w" not in self.bus.regions[name].mode:
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self.logger.info("Auto-Resizing ROM {} from {} to {}.".format(
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colorer(name),
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colorer(f"0x{self.bus.regions[name].size:x}"),
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@ -1475,13 +1475,16 @@ class LiteXSoC(SoC):
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sdram_size = min(sdram_size, size)
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# Add SDRAM region.
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self.bus.add_region("main_ram", SoCRegion(origin=self.mem_map.get("main_ram", origin), size=sdram_size))
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main_ram_region = SoCRegion(origin=self.mem_map.get("main_ram", origin),
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size=sdram_size,
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mode="rwx")
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self.bus.add_region("main_ram", main_ram_region)
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# Add CPU's direct memory buses (if not already declared) ----------------------------------
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if hasattr(self.cpu, "add_memory_buses"):
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self.cpu.add_memory_buses(
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address_width = 32,
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data_width = sdram.crossbar.controller.data_width
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address_width = 32,
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data_width = sdram.crossbar.controller.data_width
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)
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# Connect CPU's direct memory buses to LiteDRAM --------------------------------------------
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@ -78,7 +78,7 @@ class SoCCore(LiteXSoC):
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# ROM parameters
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integrated_rom_size = 0,
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integrated_rom_mode = "r",
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integrated_rom_mode = "rx",
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integrated_rom_init = [],
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# SRAM parameters
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