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integration/soc/add_ethernet: don't add timing constraints with LiteEthPHYModel.

This commit is contained in:
Florent Kermarrec 2020-11-26 09:06:06 +01:00
parent 896d1ba988
commit f390161baa
1 changed files with 8 additions and 6 deletions
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14
litex/soc/integration/soc.py
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@ -1342,6 +1342,7 @@ class LiteXSoC(SoC):
# Imports # Imports
from liteeth.core import LiteEthUDPIPCore from liteeth.core import LiteEthUDPIPCore
from liteeth.frontend.etherbone import LiteEthEtherbone from liteeth.frontend.etherbone import LiteEthEtherbone
from liteeth.phy.model import LiteEthPHYModel
# Core # Core
ethcore = LiteEthUDPIPCore( ethcore = LiteEthUDPIPCore(
phy = phy, phy = phy,
@ -1368,12 +1369,13 @@ class LiteXSoC(SoC):
else: else:
eth_rx_clk = phy.cd_eth_rx.clk eth_rx_clk = phy.cd_eth_rx.clk
eth_tx_clk = phy.cd_eth_tx.clk eth_tx_clk = phy.cd_eth_tx.clk
self.platform.add_period_constraint(eth_rx_clk, 1e9/phy.rx_clk_freq) if not isinstance(phy, LiteEthPHYModel):
self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq) self.platform.add_period_constraint(eth_rx_clk, 1e9/phy.rx_clk_freq)
self.platform.add_false_path_constraints( self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq)
self.crg.cd_sys.clk, self.platform.add_false_path_constraints(
eth_rx_clk, self.crg.cd_sys.clk,
eth_tx_clk) eth_rx_clk,
eth_tx_clk)
# Add SPI Flash -------------------------------------------------------------------------------- # Add SPI Flash --------------------------------------------------------------------------------
def add_spi_flash(self, name="spiflash", mode="4x", dummy_cycles=None, clk_freq=None): def add_spi_flash(self, name="spiflash", mode="4x", dummy_cycles=None, clk_freq=None):