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soc/cores/cpu: add riscv64-linux toolchain support for risc-v cpus. 

Toolchain can be downloaded from https://toolchains.bootlin.com/
This commit is contained in:
Florent Kermarrec 2020-01-10 08:49:23 +01:00
parent 8889821c54
commit f408527dd4
4 changed files with 7 additions and 4 deletions
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3
litex/soc/cores/cpu/minerva/core.py
View File

@ -17,7 +17,8 @@ class Minerva(CPU):
name = "minerva"
data_width = 32
endianness = "little"
gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed")
gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed",
"riscv64-linux")
linker_output_format = "elf32-littleriscv"
io_regions = {0x80000000: 0x80000000} # origin, length

3
litex/soc/cores/cpu/picorv32/core.py
View File

@ -34,7 +34,8 @@ class PicoRV32(CPU):
name = "picorv32"
data_width = 32
endianness = "little"
gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed")
gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed",
"riscv64-linux")
linker_output_format = "elf32-littleriscv"
io_regions = {0x80000000: 0x80000000} # origin, length

2
litex/soc/cores/cpu/rocket/core.py
View File

@ -67,7 +67,7 @@ class RocketRV64(CPU):
name = "rocket"
data_width = 64
endianness = "little"
gcc_triple = ("riscv64-unknown-elf")
gcc_triple = ("riscv64-unknown-elf", "riscv64-linux")
linker_output_format = "elf64-littleriscv"
io_regions = {0x10000000: 0x70000000} # origin, length

3
litex/soc/cores/cpu/vexriscv/core.py
View File

@ -78,7 +78,8 @@ class VexRiscv(CPU, AutoCSR):
name = "vexriscv"
data_width = 32
endianness = "little"
gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed")
gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed",
"riscv64-linux")
linker_output_format = "elf32-littleriscv"
io_regions = {0x80000000: 0x80000000} # origin, length