Merge pull request #1995 from VOGL-electronic/soc_spi_master_int

soc: add_spi_master: make spi_clk_freq an int
2024-06-19 19:34:31 +02:00 · 2024-06-19 19:34:31 +02:00 · f40f63ae29
parent d9854582c6 447469b0aa
commit f40f63ae29
1 changed files with 2 additions and 0 deletions
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@ -1973,6 +1973,8 @@ class LiteXSoC(SoC):

        self.check_if_exists(f"{name}")

+        spi_clk_freq = int(spi_clk_freq)
+
        if pads is None:
            pads = self.platform.request(name)