Merge pull request #1995 from VOGL-electronic/soc_spi_master_int
soc: add_spi_master: make spi_clk_freq an int
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f40f63ae29
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@ -1973,6 +1973,8 @@ class LiteXSoC(SoC):
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self.check_if_exists(f"{name}")
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self.check_if_exists(f"{name}")
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spi_clk_freq = int(spi_clk_freq)
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if pads is None:
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if pads is None:
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pads = self.platform.request(name)
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pads = self.platform.request(name)
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