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soc/cores/clock/efinix: create_clkin: adding lvds_input optional parameter (required when used with LVDS serdes)
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1 changed files with 2 additions and 2 deletions
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@ -55,7 +55,7 @@ class EFINIXPLL(LiteXModule):
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self.comb += self.platform.add_iface_io(self.name + "_rstn").eq(~self.reset)
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self.comb += self.locked.eq(self.platform.add_iface_io(self.name + "_locked"))
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def register_clkin(self, clkin, freq, name=""):
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def register_clkin(self, clkin, freq, name="", lvds_input=False):
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block = self.platform.toolchain.ifacewriter.get_block(self.name)
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block["input_clock_name"] = self.platform.get_pin_name(clkin)
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@ -79,7 +79,7 @@ class EFINIXPLL(LiteXModule):
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self.logger.error("Cannot find a pll with {} as input".format(pad_name))
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quit()
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block["input_clock"] = "EXTERNAL"
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block["input_clock"] = "EXTERNAL" if not lvds_input else "LVDS_RX"
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block["input_clock_pad"] = pin_name
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block["resource"] = pll_res
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block["clock_no"] = clock_no
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