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soc/cores/clock/efinix: create_clkin: adding lvds_input optional parameter (required when used with LVDS serdes)

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Gwenhael Goavec-Merou 2023-11-14 11:34:13 +01:00
parent 7cee8e10fd
commit f41ae88d1c
1 changed files with 2 additions and 2 deletions
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4
litex/soc/cores/clock/efinix.py
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@ -55,7 +55,7 @@ class EFINIXPLL(LiteXModule):
self.comb += self.platform.add_iface_io(self.name + "_rstn").eq(~self.reset) self.comb += self.platform.add_iface_io(self.name + "_rstn").eq(~self.reset)
self.comb += self.locked.eq(self.platform.add_iface_io(self.name + "_locked")) self.comb += self.locked.eq(self.platform.add_iface_io(self.name + "_locked"))
def register_clkin(self, clkin, freq, name=""): def register_clkin(self, clkin, freq, name="", lvds_input=False):
block = self.platform.toolchain.ifacewriter.get_block(self.name) block = self.platform.toolchain.ifacewriter.get_block(self.name)
block["input_clock_name"] = self.platform.get_pin_name(clkin) block["input_clock_name"] = self.platform.get_pin_name(clkin)
@ -79,7 +79,7 @@ class EFINIXPLL(LiteXModule):
self.logger.error("Cannot find a pll with {} as input".format(pad_name)) self.logger.error("Cannot find a pll with {} as input".format(pad_name))
quit() quit()
block["input_clock"] = "EXTERNAL" block["input_clock"] = "EXTERNAL" if not lvds_input else "LVDS_RX"
block["input_clock_pad"] = pin_name block["input_clock_pad"] = pin_name
block["resource"] = pll_res block["resource"] = pll_res
block["clock_no"] = clock_no block["clock_no"] = clock_no