Merge pull request #1070 from navan93/ibex-irq-support
Fix the support for Ibex.
This commit is contained in:
commit
f4bd729d28
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@ -124,6 +124,7 @@ class Ibex(CPU):
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self.dbus = wishbone.Interface()
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self.periph_buses = [self.ibus, self.dbus]
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self.memory_buses = []
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self.interrupt = Signal(15)
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ibus = Record(obi_layout)
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dbus = Record(obi_layout)
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@ -170,7 +171,7 @@ class Ibex(CPU):
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i_irq_software_i = 0,
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i_irq_timer_i = 0,
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i_irq_external_i = 0,
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i_irq_fast_i = 0,
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i_irq_fast_i = self.interrupt,
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i_irq_nm_i = 0,
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# Debug.
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@ -210,6 +211,7 @@ class Ibex(CPU):
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"ibex_register_file_fpga.sv",
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"ibex_wb_stage.sv",
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"ibex_core.sv",
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"ibex_top.sv"
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)
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platform.add_source(os.path.join(ibexdir, "syn", "rtl", "prim_clock_gating.v"))
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platform.add_sources(os.path.join(opentitandir, "hw", "ip", "prim", "rtl"),
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@ -217,7 +219,7 @@ class Ibex(CPU):
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"prim_assert.sv"
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)
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platform.add_verilog_include_path(os.path.join(opentitandir, "hw", "ip", "prim", "rtl"))
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platform.add_verilog_include_path(os.path.join(ibexdir, "dv", "fcov"))
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platform.add_verilog_include_path(os.path.join(opentitandir, "hw", "dv", "sv", "dv_utils"))
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def set_reset_address(self, reset_address):
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assert not hasattr(self, "reset_address")
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@ -226,4 +228,4 @@ class Ibex(CPU):
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def do_finalize(self):
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assert hasattr(self, "reset_address")
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self.specials += Instance("ibex_core", **self.cpu_params)
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self.specials += Instance("ibex_top", **self.cpu_params)
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@ -1,42 +1,55 @@
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#define MIE_MEIE 0x800
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.global main
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.global isr
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.global _start
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.global _start
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_start:
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j reset_vector
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j crt_init
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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reset_vector:
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la sp, _fstack
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la t0, trap_vector
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csrw mtvec, t0
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.balign 256
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// initialize .data
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la t0, _fdata
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la t1, _edata
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la t2, _fdata_rom
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1: beq t0, t1, 2f
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lw t3, 0(t2)
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sw t3, 0(t0)
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addi t0, t0, 4
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addi t2, t2, 4
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j 1b
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2:
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vector_table:
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j trap_entry # 0 unused
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j trap_entry # 1 unused
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j trap_entry # 2 unused
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j trap_entry # 3 software
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j trap_entry # 4 unused
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j trap_entry # 5 unused
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j trap_entry # 6 unused
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j trap_entry # 7 timer
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j trap_entry # 8 unused
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j trap_entry # 9 unused
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j trap_entry # 10 unused
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j trap_entry # 11 external
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j trap_entry # 12 unused
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j trap_entry # 13 unused
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j trap_entry # 14 unused
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j trap_entry # 15 unused
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j trap_entry # 16 firq0
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j trap_entry # 17 firq1
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j trap_entry # 18 firq2
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j trap_entry # 19 firq3
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j trap_entry # 20 firq4
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j trap_entry # 21 firq5
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j trap_entry # 22 firq6
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j trap_entry # 23 firq7
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j trap_entry # 24 firq8
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j trap_entry # 25 firq9
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j trap_entry # 26 firq10
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j trap_entry # 27 firq11
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j trap_entry # 28 firq12
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j trap_entry # 29 firq13
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j trap_entry # 30 firq14
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j trap_entry # 31 unused
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// initialize .bss
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la t0, _fbss
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la t1, _ebss
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1: beq t0, t1, 3f
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sw zero, 0(t0)
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addi t0, t0, 4
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j 1b
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3:
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// enable external interrupts
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li t0, MIE_MEIE
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csrs mie, t0
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call main
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1: j 1b
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trap_vector:
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.global trap_entry
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trap_entry:
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addi sp, sp, -16*4
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sw ra, 0*4(sp)
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sw t0, 1*4(sp)
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@ -73,3 +86,38 @@ trap_vector:
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lw t6, 15*4(sp)
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addi sp, sp, 16*4
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mret
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.text
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crt_init:
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la sp, _fstack
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la t0, vector_table
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csrw mtvec, t0
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data_init:
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la t0, _fdata
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la t1, _edata
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la t2, _fdata_rom
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data_loop:
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beq t0, t1, data_done
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lw t3, 0(t2)
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sw t3, 0(t0)
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addi t0, t0, 4
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addi t2, t2, 4
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j data_loop
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data_done:
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bss_init:
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la t0, _fbss
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la t1, _ebss
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bss_loop:
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beq t0, t1, bss_done
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sw zero, 0(t0)
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addi t0, t0, 4
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j bss_loop
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bss_done:
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call main
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infinit_loop:
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j infinit_loop
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@ -0,0 +1,14 @@
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#ifndef CSR_DEFS__H
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#define CSR_DEFS__H
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/*Reference : https://ibex-core.readthedocs.io/en/latest/03_reference/cs_registers.html# */
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#define CSR_MSTATUS_MIE 0x8
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#define CSR_IRQ_MASK 0x304
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#define CSR_IRQ_PENDING 0x344
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#define FIRQ_OFFSET 16
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#define CSR_DCACHE_INFO 0xCC0
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#endif /* CSR_DEFS__H */
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@ -1,4 +1,44 @@
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#ifndef __IRQ_H
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#define __IRQ_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <system.h>
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#include <generated/csr.h>
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static inline unsigned int irq_getie(void)
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{
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return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0;
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}
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static inline void irq_setie(unsigned int ie)
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{
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if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE);
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}
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static inline unsigned int irq_getmask(void)
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{
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unsigned int mask;
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asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_IRQ_MASK));
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return (mask >> FIRQ_OFFSET);
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}
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static inline void irq_setmask(unsigned int mask)
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{
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asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask << FIRQ_OFFSET));
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}
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static inline unsigned int irq_pending(void)
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{
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unsigned int pending;
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asm volatile ("csrr %0, %1" : "=r"(pending) : "i"(CSR_IRQ_PENDING));
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return (pending >> FIRQ_OFFSET);
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* __IRQ_H */
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@ -1,6 +1,8 @@
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#ifndef __SYSTEM_H
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#define __SYSTEM_H
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#include <csr-defs.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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@ -12,6 +14,28 @@ void flush_l2_cache(void);
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void busy_wait(unsigned int ms);
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void busy_wait_us(unsigned int us);
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#define csrr(reg) ({ unsigned long __tmp; \
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asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
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__tmp; })
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#define csrw(reg, val) ({ \
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if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
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asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
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else \
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asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
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#define csrs(reg, bit) ({ \
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if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
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asm volatile ("csrrs x0, " #reg ", %0" :: "i"(bit)); \
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else \
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asm volatile ("csrrs x0, " #reg ", %0" :: "r"(bit)); })
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#define csrc(reg, bit) ({ \
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if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
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asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \
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else \
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asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); })
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#ifdef __cplusplus
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}
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#endif
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