cores/video: Change depth parameter to format (more explicit and we'll maybe want to support other video formats).
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@ -606,12 +606,15 @@ class VideoTerminal(Module):
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class VideoFrameBuffer(Module, AutoCSR):
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"""Video FrameBuffer"""
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def __init__(self, dram_port, hres=800, vres=600, base=0x00000000, fifo_depth=65536, clock_domain="sys", clock_faster_than_sys=False, depth=32):
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def __init__(self, dram_port, hres=800, vres=600, base=0x00000000, fifo_depth=65536, clock_domain="sys", clock_faster_than_sys=False, format="rgb888"):
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self.vtg_sink = vtg_sink = stream.Endpoint(video_timing_layout)
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self.source = source = stream.Endpoint(video_data_layout)
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self.underflow = Signal()
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assert((depth == 32) or (depth == 16))
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self.depth = depth = {
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"rgb888" : 32,
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"rgb565" : 16
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}[format]
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# # #
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@ -1784,7 +1784,7 @@ class LiteXSoC(SoC):
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self.comb += vt.source.connect(phy if isinstance(phy, stream.Endpoint) else phy.sink)
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# Add Video Framebuffer ------------------------------------------------------------------------
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def add_video_framebuffer(self, name="video_framebuffer", phy=None, timings="800x600@60Hz", clock_domain="sys", depth=32):
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def add_video_framebuffer(self, name="video_framebuffer", phy=None, timings="800x600@60Hz", clock_domain="sys", format="rgb888"):
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# Imports.
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from litex.soc.cores.video import VideoTimingGenerator, VideoFrameBuffer
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@ -1802,9 +1802,9 @@ class LiteXSoC(SoC):
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hres = hres,
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vres = vres,
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base = base,
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format = format,
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clock_domain = clock_domain,
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clock_faster_than_sys = vtg.video_timings["pix_clk"] > self.sys_clk_freq,
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depth = depth
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)
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setattr(self.submodules, name, vfb)
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@ -1818,5 +1818,5 @@ class LiteXSoC(SoC):
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self.add_constant("VIDEO_FRAMEBUFFER_BASE", base)
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self.add_constant("VIDEO_FRAMEBUFFER_HRES", hres)
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self.add_constant("VIDEO_FRAMEBUFFER_VRES", vres)
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self.add_constant("VIDEO_FRAMEBUFFER_DEPTH", depth)
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self.add_constant("VIDEO_FRAMEBUFFER_DEPTH", vfb.depth)
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