adapt LiteScope to new SoC
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@ -72,6 +72,8 @@ if __name__ == "__main__":
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top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
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soc = top_class(platform, **top_kwargs)
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soc.finalize()
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memory_regions = soc.get_memory_regions()
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csr_regions = soc.get_csr_regions()
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# decode actions
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action_list = ["clean", "build-csr-csv", "build-bitstream", "load-bitstream", "all"]
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@ -130,7 +132,7 @@ RLE: {}
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subprocess.call(["rm", "-rf", "build/*"])
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if actions["build-csr-csv"]:
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csr_csv = cpuif.get_csr_csv(soc.csr_regions)
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csr_csv = cpuif.get_csr_csv(csr_regions)
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write_to_file(args.csr_csv, csr_csv)
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if actions["build-bitstream"]:
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@ -16,14 +16,15 @@ class LiteScopeSoC(SoC, AutoCSR):
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csr_map.update(SoC.csr_map)
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def __init__(self, platform):
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clk_freq = int((1/(platform.default_clk_period))*1000000000)
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self.submodules.uart2wb = LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200)
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SoC.__init__(self, platform, clk_freq, self.uart2wb,
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with_cpu=False,
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SoC.__init__(self, platform, clk_freq,
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cpu_type="none",
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with_csr=True, csr_data_width=32,
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with_uart=False,
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with_identifier=True,
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with_timer=False
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)
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self.add_cpu_or_bridge(LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200))
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self.add_wb_master(self.cpu_or_bridge.wishbone)
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self.submodules.crg = CRG(platform.request(platform.default_clk_name))
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self.submodules.io = LiteScopeIO(8)
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