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interconnect/wishbone: Revert #1505 for now sine seem to introduce some regressions. 

This will need to be understood and covered by simulations.
This commit is contained in:
Florent Kermarrec 2022-11-17 12:33:39 +01:00
parent 4b238005f7
commit f66852b975
1 changed files with 1 additions and 4 deletions
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5
litex/soc/interconnect/wishbone.py
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@ -166,8 +166,7 @@ class Arbiter(Module):
if controllers is not None: if controllers is not None:
masters = controllers masters = controllers
self.submodules.rr = roundrobin.RoundRobin(len(masters), roundrobin.SP_CE) self.submodules.rr = roundrobin.RoundRobin(len(masters))
cycs = Array(m.cyc for m in masters)
# mux master->slave signals # mux master->slave signals
for name, size, direction in _layout: for name, size, direction in _layout:
@ -186,8 +185,6 @@ class Arbiter(Module):
else: else:
self.comb += dest.eq(source) self.comb += dest.eq(source)
self.comb += self.rr.ce.eq(target.ack | ~cycs[self.rr.grant])
# connect bus requests to round-robin selector # connect bus requests to round-robin selector
reqs = [m.cyc for m in masters] reqs = [m.cyc for m in masters]
self.comb += self.rr.request.eq(Cat(*reqs)) self.comb += self.rr.request.eq(Cat(*reqs))