tb: use default runner

This commit is contained in:
Sebastien Bourdeauducq 2013-02-09 17:09:29 +01:00
parent a94ee3884f
commit f68fcef90c
6 changed files with 6 additions and 12 deletions

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@ -1,7 +1,6 @@
from migen.fhdl.structure import * from migen.fhdl.structure import *
from migen.bus.asmibus import * from migen.bus.asmibus import *
from migen.sim.generic import Simulator, TopLevel from migen.sim.generic import Simulator, TopLevel
from migen.sim.icarus import Runner
from milkymist.asmicon import * from milkymist.asmicon import *
@ -33,7 +32,7 @@ def main():
fragment = dut.get_fragment() + initiator1.get_fragment() + initiator2.get_fragment() + \ fragment = dut.get_fragment() + initiator1.get_fragment() + initiator2.get_fragment() + \
logger.get_fragment() + \ logger.get_fragment() + \
Fragment(sim=[end_simulation]) Fragment(sim=[end_simulation])
sim = Simulator(fragment, Runner(), TopLevel("my.vcd")) sim = Simulator(fragment, TopLevel("my.vcd"))
sim.run(700) sim.run(700)
main() main()

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@ -1,7 +1,6 @@
from migen.fhdl.structure import * from migen.fhdl.structure import *
from migen.bus import wishbone, wishbone2asmi, asmibus from migen.bus import wishbone, wishbone2asmi, asmibus
from migen.sim.generic import Simulator, TopLevel from migen.sim.generic import Simulator, TopLevel
from migen.sim.icarus import Runner
from milkymist.asmicon import * from milkymist.asmicon import *
@ -41,7 +40,7 @@ def main():
conn.get_fragment() + \ conn.get_fragment() + \
logger.get_fragment() + \ logger.get_fragment() + \
Fragment(sim=[end_simulation]) Fragment(sim=[end_simulation])
sim = Simulator(fragment, Runner(), TopLevel("my.vcd")) sim = Simulator(fragment, TopLevel("my.vcd"))
sim.run() sim.run()
main() main()

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@ -1,7 +1,6 @@
from migen.fhdl.structure import * from migen.fhdl.structure import *
from migen.bus.asmibus import * from migen.bus.asmibus import *
from migen.sim.generic import Simulator, TopLevel from migen.sim.generic import Simulator, TopLevel
from migen.sim.icarus import Runner
from milkymist.asmicon.bankmachine import * from milkymist.asmicon.bankmachine import *
@ -42,7 +41,7 @@ def main():
fragment = hub.get_fragment() + initiator.get_fragment() + \ fragment = hub.get_fragment() + initiator.get_fragment() + \
dut.get_fragment() + logger.get_fragment() + completer.get_fragment() + \ dut.get_fragment() + logger.get_fragment() + completer.get_fragment() + \
Fragment(sim=[end_simulation]) Fragment(sim=[end_simulation])
sim = Simulator(fragment, Runner(), TopLevel("my.vcd")) sim = Simulator(fragment, TopLevel("my.vcd"))
sim.run() sim.run()
main() main()

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@ -2,7 +2,6 @@ from random import Random
from migen.fhdl.structure import * from migen.fhdl.structure import *
from migen.sim.generic import Simulator, TopLevel from migen.sim.generic import Simulator, TopLevel
from migen.sim.icarus import Runner
from milkymist.asmicon.refresher import * from milkymist.asmicon.refresher import *
@ -44,7 +43,7 @@ def main():
logger = CommandLogger(dut.cmd) logger = CommandLogger(dut.cmd)
granter = Granter(dut.req, dut.ack) granter = Granter(dut.req, dut.ack)
fragment = dut.get_fragment() + logger.get_fragment() + granter.get_fragment() fragment = dut.get_fragment() + logger.get_fragment() + granter.get_fragment()
sim = Simulator(fragment, Runner()) sim = Simulator(fragment)
sim.run(400) sim.run(400)
main() main()

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@ -3,7 +3,6 @@ from random import Random
from migen.fhdl.structure import * from migen.fhdl.structure import *
from migen.bus.asmibus import * from migen.bus.asmibus import *
from migen.sim.generic import Simulator, TopLevel from migen.sim.generic import Simulator, TopLevel
from migen.sim.icarus import Runner
from milkymist.asmicon.bankmachine import _AddressSlicer, _SimpleSelector from milkymist.asmicon.bankmachine import _AddressSlicer, _SimpleSelector
@ -71,7 +70,7 @@ def main():
fragment = hub.get_fragment() + sum([i.get_fragment() for i in initiators], Fragment()) + \ fragment = hub.get_fragment() + sum([i.get_fragment() for i in initiators], Fragment()) + \
logger.get_fragment() + selector.get_fragment() + completer.get_fragment() + \ logger.get_fragment() + selector.get_fragment() + completer.get_fragment() + \
Fragment(sim=[end_simulation]) Fragment(sim=[end_simulation])
sim = Simulator(fragment, Runner(), TopLevel("my.vcd")) sim = Simulator(fragment, TopLevel("my.vcd"))
sim.run() sim.run()
main() main()

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@ -1,7 +1,6 @@
from migen.fhdl.structure import * from migen.fhdl.structure import *
from migen.bus import asmibus from migen.bus import asmibus
from migen.sim.generic import Simulator from migen.sim.generic import Simulator
from migen.sim.icarus import Runner
from milkymist.framebuffer import * from milkymist.framebuffer import *
@ -13,7 +12,7 @@ def main():
dut = Framebuffer(1, port, True) dut = Framebuffer(1, port, True)
fragment = hub.get_fragment() + dut.get_fragment() fragment = hub.get_fragment() + dut.get_fragment()
sim = Simulator(fragment, Runner()) sim = Simulator(fragment)
sim.run(1) sim.run(1)
def csr_w(addr, d): def csr_w(addr, d):