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cores/cpu/vexriscv_smp fix argument parsing

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Dolu1990 2020-08-13 12:52:05 +02:00 committed by GitHub
parent 0e480dd662
commit f730f1d7ba
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1 changed files with 4 additions and 4 deletions
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litex/soc/cores/cpu/vexriscv_smp/core.py
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@ -70,10 +70,10 @@ class VexRiscvSMP(CPU):
if(args.without_coherent_dma): VexRiscvSMP.coherent_dma = bool(False) if(args.without_coherent_dma): VexRiscvSMP.coherent_dma = bool(False)
if(args.dcache_width): VexRiscvSMP.dcache_width = int(args.dcache_width) if(args.dcache_width): VexRiscvSMP.dcache_width = int(args.dcache_width)
if(args.icache_width): VexRiscvSMP.icache_width = int(args.icache_width) if(args.icache_width): VexRiscvSMP.icache_width = int(args.icache_width)
if(args.icache_width): VexRiscvSMP.dcache_size = int(args.dcache_size) if(args.dcache_size): VexRiscvSMP.dcache_size = int(args.dcache_size)
if(args.icache_width): VexRiscvSMP.icache_size = int(args.icache_size) if(args.icache_size): VexRiscvSMP.icache_size = int(args.icache_size)
if(args.icache_width): VexRiscvSMP.dcache_ways = int(args.dcache_ways) if(args.dcache_ways): VexRiscvSMP.dcache_ways = int(args.dcache_ways)
if(args.icache_width): VexRiscvSMP.icache_ways = int(args.icache_ways) if(args.icache_ways): VexRiscvSMP.icache_ways = int(args.icache_ways)
@property @property
def mem_map(self): def mem_map(self):