cores/cpus: Generate all CPU configs as LiteX configs (for consistency).
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@ -301,7 +301,7 @@ class NaxRiscv(CPU):
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soc.add_memory_region("opensbi", self.mem_map["main_ram"] + 0x00f0_0000, 0x8_0000, type="cached+linker")
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soc.add_memory_region("opensbi", self.mem_map["main_ram"] + 0x00f0_0000, 0x8_0000, type="cached+linker")
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# Define ISA.
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# Define ISA.
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soc.add_constant("CPU_ISA", NaxRiscv.get_arch())
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soc.add_config("CPU_ISA", NaxRiscv.get_arch())
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# Add PLIC Bus (AXILite Slave).
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# Add PLIC Bus (AXILite Slave).
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self.plicbus = plicbus = axi.AXILiteInterface(address_width=32, data_width=32)
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self.plicbus = plicbus = axi.AXILiteInterface(address_width=32, data_width=32)
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@ -367,7 +367,7 @@ class Rocket(CPU):
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# Define number of CPUs
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# Define number of CPUs
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soc.add_config("CPU_COUNT", num_cores)
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soc.add_config("CPU_COUNT", num_cores)
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soc.add_constant("CPU_ISA", self.get_arch(self.variant))
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soc.add_config("CPU_ISA", self.get_arch(self.variant))
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def do_finalize(self):
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def do_finalize(self):
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assert hasattr(self, "reset_address")
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assert hasattr(self, "reset_address")
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@ -401,24 +401,24 @@ class VexRiscvSMP(CPU):
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# Define number of CPUs
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# Define number of CPUs
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soc.add_config("CPU_COUNT", VexRiscvSMP.cpu_count)
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soc.add_config("CPU_COUNT", VexRiscvSMP.cpu_count)
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soc.add_constant("CPU_ISA", VexRiscvSMP.get_arch())
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soc.add_config("CPU_ISA", VexRiscvSMP.get_arch())
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# Constants for cache so we can add them in the DTS.
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# Constants for cache so we can add them in the DTS.
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if (VexRiscvSMP.dcache_size > 0):
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if (VexRiscvSMP.dcache_size > 0):
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soc.add_constant("cpu_dcache_size", VexRiscvSMP.dcache_size)
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soc.add_config("CPU_DCACHE_SIZE", VexRiscvSMP.dcache_size)
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soc.add_constant("cpu_dcache_ways", VexRiscvSMP.dcache_ways)
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soc.add_config("CPU_DCACHE_WAYS", VexRiscvSMP.dcache_ways)
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soc.add_constant("cpu_dcache_block_size", 64) # hardwired?
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soc.add_config("CPU_DCACHE_BLOCK_SIZE", 64) # hardwired?
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if (VexRiscvSMP.icache_size > 0):
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if (VexRiscvSMP.icache_size > 0):
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soc.add_constant("cpu_icache_size", VexRiscvSMP.icache_size)
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soc.add_config("CPU_ICACHE_SIZE", VexRiscvSMP.icache_size)
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soc.add_constant("cpu_icache_ways", VexRiscvSMP.icache_ways)
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soc.add_config("CPU_ICACHE_WAYS", VexRiscvSMP.icache_ways)
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soc.add_constant("cpu_icache_block_size", 64) # hardwired?
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soc.add_config("CPU_ICACHE_BLOCK_SIZE", 64) # hardwired?
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# Constants for TLB so we can add them in the DTS
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# Constants for TLB so we can add them in the DTS
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# full associative so only the size is described.
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# full associative so only the size is described.
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if (VexRiscvSMP.dtlb_size > 0):
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if (VexRiscvSMP.dtlb_size > 0):
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soc.add_constant("cpu_dtlb_size", VexRiscvSMP.dtlb_size)
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soc.add_config("CPU_DTLB_SIZE", VexRiscvSMP.dtlb_size)
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soc.add_constant("cpu_dtlb_ways", VexRiscvSMP.dtlb_size)
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soc.add_config("CPU_DTLB_WAYS", VexRiscvSMP.dtlb_size)
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if (VexRiscvSMP.itlb_size > 0):
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if (VexRiscvSMP.itlb_size > 0):
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soc.add_constant("cpu_itlb_size", VexRiscvSMP.itlb_size)
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soc.add_config("CPU_ITLB_SIZE", VexRiscvSMP.itlb_size)
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soc.add_constant("cpu_itlb_ways", VexRiscvSMP.itlb_size)
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soc.add_config("CPU_ITLB_WAYS", VexRiscvSMP.itlb_size)
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# Add PLIC as Bus Slave
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# Add PLIC as Bus Slave
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self.plicbus = plicbus = wishbone.Interface()
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self.plicbus = plicbus = wishbone.Interface()
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