wishbone: add Cache (from WB2LASMI)
This commit is contained in:
Florent Kermarrec
parent
6e876c63ad
commit
f8b1152b98
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@ -1,8 +1,10 @@
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from migen.fhdl.std import *
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from migen.genlib import roundrobin
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from migen.genlib.record import *
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from migen.genlib.misc import optree, chooser, FlipFlop, Counter
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from migen.genlib.misc import split, displacer, optree, chooser
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from migen.genlib.misc import FlipFlop, Counter
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from migen.genlib.fsm import FSM, NextState
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from migen.bank.description import *
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from migen.bus.transactions import *
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_layout = [
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@ -407,6 +409,162 @@ class Converter(Module):
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Record.connect(master, slave)
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class Cache(Module, AutoCSR):
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"""Cache
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This module is a write-back wishbone cache that can be used as a L2 cache.
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Cachesize (in 32-bit words) is the size of the data store and must be a power of 2
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"""
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def __init__(self, cachesize, master, slave):
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self._size = CSRStatus(8, reset=log2_int(cachesize))
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self.master = master
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self.slave = slave
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###
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dw_from = flen(master.dat_r)
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dw_to = flen(slave.dat_r)
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if dw_to > dw_from and (dw_to % dw_from) != 0:
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raise ValueError("Slave data width must be a multiple of {dw}".format(dw=dw_from))
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if dw_to < dw_from and (dw_from % dw_to) != 0:
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raise ValueError("Master data width must be a multiple of {dw}".format(dw=dw_to))
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# Split address:
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# TAG | LINE NUMBER | LINE OFFSET
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offsetbits = log2_int(max(dw_to//dw_from, 1))
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addressbits = flen(slave.adr) + offsetbits
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linebits = log2_int(cachesize) - offsetbits
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tagbits = addressbits - linebits
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wordbits = log2_int(max(dw_from//dw_to, 1))
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adr_offset, adr_line, adr_tag = split(master.adr, offsetbits, linebits, tagbits)
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word = Signal(wordbits) if wordbits else None
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# Data memory
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data_mem = Memory(dw_to*2**wordbits, 2**linebits)
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data_port = data_mem.get_port(write_capable=True, we_granularity=8)
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self.specials += data_mem, data_port
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write_from_slave = Signal()
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if adr_offset is None:
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adr_offset_r = None
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else:
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adr_offset_r = Signal(offsetbits)
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self.sync += adr_offset_r.eq(adr_offset)
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self.comb += [
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data_port.adr.eq(adr_line),
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If(write_from_slave,
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displacer(slave.dat_r, word, data_port.dat_w),
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displacer(Replicate(1, dw_to//8), word, data_port.we)
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).Else(
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data_port.dat_w.eq(Replicate(master.dat_w, max(dw_to//dw_from, 1))),
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If(master.cyc & master.stb & master.we & master.ack,
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displacer(master.sel, adr_offset, data_port.we, 2**offsetbits, reverse=True)
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)
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),
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chooser(data_port.dat_r, word, slave.dat_w),
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slave.sel.eq(2**(dw_to//8)-1),
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chooser(data_port.dat_r, adr_offset_r, master.dat_r, reverse=True)
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]
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# Tag memory
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tag_layout = [("tag", tagbits), ("dirty", 1)]
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tag_mem = Memory(layout_len(tag_layout), 2**linebits)
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tag_port = tag_mem.get_port(write_capable=True)
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self.specials += tag_mem, tag_port
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tag_do = Record(tag_layout)
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tag_di = Record(tag_layout)
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self.comb += [
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tag_do.raw_bits().eq(tag_port.dat_r),
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tag_port.dat_w.eq(tag_di.raw_bits())
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]
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self.comb += [
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tag_port.adr.eq(adr_line),
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tag_di.tag.eq(adr_tag)
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]
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if word is not None:
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self.comb += slave.adr.eq(Cat(word, adr_line, tag_do.tag))
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else:
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self.comb += slave.adr.eq(Cat(adr_line, tag_do.tag))
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# slave word computation, word_clr and word_inc will be simplified
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# at synthesis when wordbits=0
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word_clr = Signal()
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word_inc = Signal()
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if word is not None:
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self.sync += \
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If(word_clr,
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word.eq(0),
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).Elif(word_inc,
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word.eq(word+1)
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)
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def word_is_last(word):
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if word is not None:
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return word == 2**wordbits-1
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else:
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return 1
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# Control FSM
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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If(master.cyc & master.stb,
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NextState("TEST_HIT")
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)
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)
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fsm.act("TEST_HIT",
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word_clr.eq(1),
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If(tag_do.tag == adr_tag,
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master.ack.eq(1),
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If(master.we,
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tag_di.dirty.eq(1),
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tag_port.we.eq(1)
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),
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NextState("IDLE")
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).Else(
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If(tag_do.dirty,
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NextState("EVICT")
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).Else(
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NextState("REFILL_WRTAG")
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)
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)
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)
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fsm.act("EVICT",
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slave.stb.eq(1),
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slave.cyc.eq(1),
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slave.we.eq(1),
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If(slave.ack,
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word_inc.eq(1),
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If(word_is_last(word),
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NextState("REFILL_WRTAG")
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)
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)
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)
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fsm.act("REFILL_WRTAG",
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# Write the tag first to set the slave address
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tag_port.we.eq(1),
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word_clr.eq(1),
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NextState("REFILL")
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)
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fsm.act("REFILL",
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slave.stb.eq(1),
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slave.cyc.eq(1),
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slave.we.eq(0),
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If(slave.ack,
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write_from_slave.eq(1),
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word_inc.eq(1),
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If(word_is_last(word),
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NextState("TEST_HIT"),
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).Else(
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NextState("REFILL")
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)
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)
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)
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class Tap(Module):
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def __init__(self, bus, handler=print):
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self.bus = bus
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