Merge pull request #1972 from motec-research/dts_all_soc_sys_clk
tools/litex_json2dts_linux: add all soc sys_clk
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f8cee3836d
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@ -118,13 +118,18 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic
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# Clocks ------------------------------------------------------------------------------------------
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# Clocks ------------------------------------------------------------------------------------------
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dts += """
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for c in [c for c in d["constants"].keys() if c.endswith("config_clock_frequency")]:
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sys_clk: pll {{
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name = c.removesuffix("config_clock_frequency") + "sys_clk"
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dts += """
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{name}: clock-{freq} {{
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compatible = "fixed-clock";
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compatible = "fixed-clock";
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#clock-cells = <0>;
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#clock-cells = <0>;
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clock-frequency = <{sys_clk_freq}>;
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clock-frequency = <{freq}>;
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}};
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}};
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""".format(sys_clk_freq=d["constants"]["config_clock_frequency"])
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""".format(
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name=name,
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freq=d["constants"][c],
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)
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# CPU ------------------------------------------------------------------------------------------
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# CPU ------------------------------------------------------------------------------------------
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