Wishbone: omit fixed LSBs
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570ea8ccf8
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@ -8,7 +8,7 @@ class Inst:
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self.interrupt = Signal(BV(32))
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self.ext_break = Signal()
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self._inst = Instance("lm32_top",
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[("I_ADR_O", i.adr_o),
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[("I_ADR_O", BV(32)),
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("I_DAT_O", i.dat_o),
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("I_SEL_O", i.sel_o),
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("I_CYC_O", i.cyc_o),
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@ -17,7 +17,7 @@ class Inst:
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("I_CTI_O", i.cti_o),
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("I_LOCK_O", BV(1)),
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("I_BTE_O", i.bte_o),
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("D_ADR_O", d.adr_o),
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("D_ADR_O", BV(32)),
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("D_DAT_O", d.dat_o),
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("D_SEL_O", d.sel_o),
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("D_CYC_O", d.cyc_o),
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@ -44,6 +44,8 @@ class Inst:
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def get_fragment(self):
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comb = [
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self._inst.ins["I_RTY_I"].eq(0),
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self._inst.ins["D_RTY_I"].eq(0)
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self._inst.ins["D_RTY_I"].eq(0),
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self.ibus.adr_o.eq(self._inst.outs["I_ADR_O"][2:]),
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self.dbus.adr_o.eq(self._inst.outs["D_ADR_O"][2:])
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]
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return Fragment(comb=comb, instances=[self._inst])
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@ -11,10 +11,10 @@ class Inst:
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self.we_n = Signal()
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self.ce_n = Signal()
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self.timeline = timeline.Inst(self.bus.cyc_i & self.bus.stb_i,
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[(0, [self.adr.eq(Cat(0, self.bus.adr_i[2:adr_width]))]),
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[(0, [self.adr.eq(Cat(0, self.bus.adr_i[:adr_width-2]))]),
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(rd_timing, [
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self.bus.dat_o[16:].eq(self.d),
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self.adr.eq(Cat(1, self.bus.adr_i[2:adr_width]))]),
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self.adr.eq(Cat(1, self.bus.adr_i[:adr_width-2]))]),
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(2*rd_timing, [
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self.bus.dat_o[:16].eq(self.d),
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self.bus.ack_o.eq(1)]),
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