soc/cores/i2c: rewrite state machine
* Fix READ: was reading too many bits * CLeaner transitions between states: ACK=>IDLE with scl=0. Other to IDLE with scl=1 * Now cleanly supports RESTART * conceptual support for compound commands - not exposed yet * fix tests: now appears to be I2C compliant
This commit is contained in:
Andrew Dennison
parent
13811aeacb
commit
f99658200e
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@ -65,41 +65,57 @@ class I2CMasterMachine(LiteXModule):
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self.fsm = fsm
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fsm.act("IDLE",
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If(self.start,
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NextState("START0"),
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).Elif(self.stop & self.start,
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NextState("RESTART0"),
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).Elif(self.stop,
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# Valid combinations (lowest to highest priority):
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# stop: lowest priority
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# read (& optional stop with automatic NACK)
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# write (& optional stop)
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# start (indicates start or restart)
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# start & write (& optional stop)
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# start & write & read (& optional stop)
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# lowest priority
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# *** TODO: support compound commands with I2CMaster ***
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If(self.stop & ~self.scl_o,
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# stop is only valid after an ACK
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NextState("STOP0"),
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).Elif(self.write,
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),
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If(self.read,
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# post decrement so read first bit and shift in 7
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NextValue(bits, 8-1),
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NextState("READ0"),
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),
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If(self.write,
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NextValue(bits, 8),
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NextState("WRITE0"),
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).Elif(self.read,
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NextValue(bits, 8),
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NextState("READ0"),
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)
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),
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# start could be requesting a restart
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If(self.start,
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NextState("RESTART0"),
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),
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# highest priority: start only if scl is high
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If(self.start & self.scl_o,
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NextState("START0"),
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),
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)
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fsm.act("START0",
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NextValue(self.scl_o, 1),
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NextState("START1"))
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fsm.act("START1",
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# Always entered with scl_o = 1
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NextValue(self.sda_o, 0),
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NextState("IDLE"))
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fsm.act("RESTART0",
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NextValue(self.scl_o, 0),
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# Only entered from IDLE with scl_o = 0
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NextValue(self.sda_o, 1),
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NextState("RESTART1"))
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fsm.act("RESTART1",
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NextValue(self.sda_o, 1),
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NextValue(self.scl_o, 1),
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NextState("START0"))
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fsm.act("STOP0",
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NextValue(self.scl_o, 0),
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# Only entered from IDLE with scl_o = 0
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NextValue(self.sda_o, 0),
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NextState("STOP1"))
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fsm.act("STOP1",
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NextValue(self.scl_o, 1),
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NextValue(self.sda_o, 0),
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NextState("STOP2"))
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fsm.act("STOP2",
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NextValue(self.sda_o, 1),
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@ -126,13 +142,15 @@ class I2CMasterMachine(LiteXModule):
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NextState("READACK1"),
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)
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fsm.act("READACK1",
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# ACK => IDLE always with scl_o = 0
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NextValue(self.scl_o, 0),
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NextValue(self.ack, ~self.sda_i),
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NextState("IDLE")
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)
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fsm.act("READ0",
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NextValue(self.scl_o, 0),
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NextValue(self.sda_o, 1),
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# ACK => IDLE => READ0 always with scl_o = 0
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NextValue(self.scl_o, 1),
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NextState("READ1"),
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)
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fsm.act("READ1",
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@ -154,7 +172,13 @@ class I2CMasterMachine(LiteXModule):
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)
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fsm.act("WRITEACK0",
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NextValue(self.scl_o, 1),
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NextState("IDLE"),
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NextState("WRITEACK1"),
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)
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fsm.act("WRITEACK1",
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# ACK => IDLE always with scl_o = 0
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NextValue(self.scl_o, 0),
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NextValue(self.sda_o, 1),
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NextState("IDLE")
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)
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run = Signal()
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@ -78,7 +78,7 @@ class TestI2C(unittest.TestCase):
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pads = _MockPads()
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dut = I2CMaster(pads)
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def check_trans(scl, sda):
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def check_trans(scl, sda, msg=""):
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scl, sda = int(scl), int(sda)
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scl_init, sda_init = (yield dut.scl_t.i), (yield dut.sda_t.i)
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timeout = 0
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@ -88,7 +88,7 @@ class TestI2C(unittest.TestCase):
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return
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timeout += 1
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self.assertLess(timeout, 20,
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"\n*** timeout waiting for: " +
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f"\n*** {msg} timeout. Waiting for: " +
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f"scl:{scl_now} checking:{scl_init}=>{scl} " +
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f"sda:{sda_now} checking:{sda_init}=>{sda} ***"
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)
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@ -116,11 +116,11 @@ class TestI2C(unittest.TestCase):
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yield from wait_idle()
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def read_bit(value):
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#print(f"read_bit:{value}")
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yield from check_trans(scl=False, sda=(yield dut.sda_tristate.i_mock))
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print(f"read_bit:{value}")
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yield dut.sda_tristate.i_mock.eq(value)
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yield from check_trans(scl=True, sda=value)
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# need to restore i_mock elsewhere
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yield from check_trans(scl=True, sda=value)
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yield from check_trans(scl=False, sda=value)
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yield dut.sda_tristate.i_mock.eq(True)
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def read_ack(value):
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#print(f"read_ack:{value}")
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@ -132,6 +132,28 @@ class TestI2C(unittest.TestCase):
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ack = ((yield from dut.bus.read(I2C_XFER_ADDR)) & I2C_ACK) != 0
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self.assertEqual(ack, value)
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def i2c_restart():
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yield from check_trans(scl=False, sda=True, msg="checking restart precondition")
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yield from dut.bus.write(I2C_XFER_ADDR, I2C_START)
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yield from check_trans(scl=False, sda=True, msg="checking restart0")
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yield from check_trans(scl=True, sda=True, msg="checking restart1")
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yield from check_trans(scl=True, sda=False, msg="checking start0")
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yield from wait_idle()
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def i2c_start():
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yield from check_trans(scl=True, sda=True, msg="checking start precondition")
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yield from dut.bus.write(I2C_XFER_ADDR, I2C_START)
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yield from check_trans(scl=True, sda=False, msg="checking start0")
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yield from wait_idle()
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def i2c_stop():
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yield from check_trans(scl=False, sda=True, msg="checking stop after read or write")
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yield from dut.bus.write(I2C_XFER_ADDR, I2C_STOP)
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yield from check_trans(scl=False, sda=False, msg="checking STOP0")
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yield from check_trans(scl=True, sda=False, msg="checking STOP1")
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yield from check_trans(scl=True, sda=True, msg="checking STOP2")
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yield from wait_idle()
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def i2c_write(value, ack=True):
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value = int(value)
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test_bin = '{0:08b}'.format(value)
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@ -144,7 +166,7 @@ class TestI2C(unittest.TestCase):
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def i2c_read(value, ack=True):
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value = int(value)
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test_bin = '{0:08b}'.format(value)
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#print(f"I2C_READ | {hex(value)}:0x{test_bin}")
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print(f"I2C_READ | {hex(value)}:0x{test_bin}")
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yield from dut.bus.write(I2C_XFER_ADDR, I2C_READ | (I2C_ACK if ack else 0))
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for i in list(test_bin):
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yield from read_bit(int(i))
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@ -159,23 +181,23 @@ class TestI2C(unittest.TestCase):
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data = (yield from dut.bus.read(I2C_CONFIG_ADDR)) & 0xff
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self.assertEqual(data, 4)
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yield from dut.bus.write(I2C_XFER_ADDR, I2C_START)
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yield from check_trans(scl=True, sda=False)
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yield from wait_idle()
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yield from i2c_write(0x82)
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print("write 1 byte 0x18 to address 0x41")
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yield from i2c_start()
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yield from i2c_write(0x41<<1 | 0)
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yield from i2c_write(0x18, ack=False)
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yield from i2c_stop()
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yield from dut.bus.write(I2C_XFER_ADDR, I2C_START | I2C_STOP)
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yield from check_trans(scl=True, sda=False)
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yield from wait_idle()
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print("read 1 byte from address 0x41")
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yield from i2c_start()
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yield from i2c_write(0x41<<1 | 1)
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yield from i2c_read(0x18, ack=False)
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yield from i2c_read(0x88)
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yield from dut.bus.write(I2C_XFER_ADDR, I2C_STOP)
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yield from check_trans(scl=False, sda=False)
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yield from wait_idle()
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print("read 2 bytes from address 0x55")
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yield from i2c_restart()
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yield from i2c_write(0x55<<1 | 1)
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yield from i2c_read(0xDE, ack=True)
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yield from i2c_read(0xAD, ack=False)
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yield from i2c_stop()
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clocks = {
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"sys": 10,
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