bus: add DFI
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@ -367,6 +367,8 @@ slave interfaces of the following buses:
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software.
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software.
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- ASMIbus, a split-transaction bus optimized for use with a
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- ASMIbus, a split-transaction bus optimized for use with a
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high-performance, out-of-order SDRAM controller.
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high-performance, out-of-order SDRAM controller.
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- DFI [12] (partial), a standard interface protocol between memory
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controller logic and PHY interfaces.
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It also provides interconnect components for these buses, such as
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It also provides interconnect components for these buses, such as
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arbiters and address decoders. The strength of the Migen procedurally
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arbiters and address decoders. The strength of the Migen procedurally
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@ -476,3 +478,4 @@ References:
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[ 9] http://orc-apps.sourceforge.net/
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[ 9] http://orc-apps.sourceforge.net/
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[10] http://opendf.sourceforge.net/
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[10] http://opendf.sourceforge.net/
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[11] http://networkx.lanl.gov/
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[11] http://networkx.lanl.gov/
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[12] http://www.ddr-phy.org/
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@ -0,0 +1,54 @@
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from migen.fhdl.structure import *
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from migen.bus.simple import *
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def phase_description(a, ba, d):
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return Description(
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(M_TO_S, "address", a),
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(M_TO_S, "bank", ba),
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(M_TO_S, "cas_n", 1),
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(M_TO_S, "cke", 1),
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(M_TO_S, "cs_n", 1),
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(M_TO_S, "ras_n", 1),
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(M_TO_S, "we_n", 1),
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(M_TO_S, "wrdata", d),
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(M_TO_S, "wrdata_en", 1),
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(M_TO_S, "wrdata_mask", d//8),
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(M_TO_S, "rddata_en", 1),
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(S_TO_M, "rddata", d),
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(S_TO_M, "rddata_valid", 1)
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)
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class Interface:
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def __init__(self, a, ba, d, nphases=1):
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self.pdesc = phase_description(a, ba, d)
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self.phases = [SimpleInterface(self.pdesc) for i in range(nphases)]
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# Returns pairs (DFI-mandated signal name, Migen signal object)
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def get_standard_names(self):
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r = []
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add_suffix = len(self.phases) > 1
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for n, phase in enumerate(self.phases):
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for signal in self.pdesc.desc:
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if add_suffix:
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if signal[0] == M_TO_S:
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suffix = "_p" + int(n)
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else:
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suffix = "_w" + int(n)
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else:
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suffix = ""
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r.append(("dfi_" + signal[1] + suffix, getattr(self, signal[1])))
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return r
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class Interconnect:
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def __init__(self, master, slave):
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self.master = master
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self.slave = slave
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def get_fragment(self):
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f = Fragment()
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for pm, ps in zip(self.master.phases, self.slave.phases):
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ic = SimpleInterconnect(pm, [ps])
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f += ic.get_fragment()
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return f
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