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integration/soc/jtag: Switch JTAGPHY to sys_clk/simplify.

This commit is contained in:
Florent Kermarrec 2023-12-13 09:24:23 +01:00
parent 4e57cca85f
commit faae1ea95a
1 changed files with 1 additions and 4 deletions
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5
litex/soc/integration/soc.py
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@ -1440,10 +1440,7 @@ class LiteXSoC(SoC):
# JTAG UART. # JTAG UART.
elif uart_name in ["jtag_uart"]: elif uart_name in ["jtag_uart"]:
from litex.soc.cores.jtag import JTAGPHY from litex.soc.cores.jtag import JTAGPHY
# Run JTAG-UART in sys_jtag clk domain similar to sys clk domain but without sys_rst. uart_phy = JTAGPHY(device=self.platform.device, platform=self.platform)
self.cd_sys_jtag = ClockDomain()
self.comb += self.cd_sys_jtag.clk.eq(ClockSignal("sys"))
uart_phy = JTAGPHY(device=self.platform.device, clock_domain="sys_jtag", platform=self.platform)
uart = UART(uart_phy, **uart_kwargs) uart = UART(uart_phy, **uart_kwargs)
# Sim. # Sim.