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cpu/minerva: add workaround on import until code is released

This commit is contained in:
Florent Kermarrec 2018-09-06 16:40:30 +02:00
parent 9cfae4dfde
commit fb24ac0ecc
1 changed files with 12 additions and 9 deletions
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7
litex/soc/cores/cpu/minerva/core.py
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@ -4,8 +4,6 @@ from migen import *
from litex.soc.interconnect import wishbone from litex.soc.interconnect import wishbone
from minerva.core import Minerva as MinervaCPU
class Minerva(Module): class Minerva(Module):
def __init__(self, platform, cpu_reset_address, variant=None): def __init__(self, platform, cpu_reset_address, variant=None):
@ -17,6 +15,8 @@ class Minerva(Module):
### ###
try: # FIXME: workaround until Minerva code is released
from minerva.core import Minerva as MinervaCPU
self.submodules.cpu = MinervaCPU(reset_address=cpu_reset_address) self.submodules.cpu = MinervaCPU(reset_address=cpu_reset_address)
self.comb += [ self.comb += [
self.cpu.reset.eq(self.reset), self.cpu.reset.eq(self.reset),
@ -24,3 +24,6 @@ class Minerva(Module):
self.cpu.ibus.connect(self.ibus), self.cpu.ibus.connect(self.ibus),
self.cpu.dbus.connect(self.dbus) self.cpu.dbus.connect(self.dbus)
] ]
except:
pass