cpu/minerva: add workaround on import until code is released

litex/soc/cores/cpu/minerva/core.py

@@ -4,8 +4,6 @@ from migen import *
 
 from litex.soc.interconnect import wishbone
 
-from minerva.core import Minerva as MinervaCPU
-
 
 class Minerva(Module):
     def __init__(self, platform, cpu_reset_address, variant=None):
@@ -17,6 +15,8 @@ class Minerva(Module):
 
         ###
 
+        try: # FIXME: workaround until Minerva code is released
+            from minerva.core import Minerva as MinervaCPU
             self.submodules.cpu = MinervaCPU(reset_address=cpu_reset_address)
             self.comb += [
                 self.cpu.reset.eq(self.reset),
@@ -24,3 +24,6 @@ class Minerva(Module):
                 self.cpu.ibus.connect(self.ibus),
                 self.cpu.dbus.connect(self.dbus)
             ]
+        except:
+            pass
+