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integration/soc/add_uart: add crossover+bridge support. 

Useful to have both CPU UART and bridge debug capability.
This commit is contained in:
Florent Kermarrec 2020-12-10 18:32:21 +01:00
parent 88bd754dd6
commit fb3b09db15
1 changed files with 7 additions and 0 deletions
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7
litex/soc/integration/soc.py
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@ -1100,6 +1100,13 @@ class LiteXSoC(SoC):
tx_fifo_depth = fifo_depth, tx_fifo_depth = fifo_depth,
rx_fifo_depth = fifo_depth) rx_fifo_depth = fifo_depth)
# Crossover + Bridge
elif name in ["crossover+bridge"]:
self.add_uartbone(baudrate=baudrate)
self.submodules.uart = uart.UARTCrossover(
tx_fifo_depth = fifo_depth,
rx_fifo_depth = fifo_depth)
# Model/Sim # Model/Sim
elif name in ["model", "sim"]: elif name in ["model", "sim"]:
self.submodules.uart_phy = uart.RS232PHYModel(self.platform.request("serial")) self.submodules.uart_phy = uart.RS232PHYModel(self.platform.request("serial"))