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Use new memory port API

This commit is contained in:
Sebastien Bourdeauducq 2013-05-28 15:56:14 +02:00
parent 611c4192b1
commit fb3e61230b
3 changed files with 5 additions and 2 deletions
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2
milkymist/dvisampler/chansync.py
View File

@ -21,6 +21,7 @@ class _SyncBuffer(Module):
self.specials += storage self.specials += storage
wrport = storage.get_port(write_capable=True) wrport = storage.get_port(write_capable=True)
self.specials += wrport
self.comb += [ self.comb += [
wrport.adr.eq(produce), wrport.adr.eq(produce),
wrport.dat_w.eq(self.din), wrport.dat_w.eq(self.din),
@ -29,6 +30,7 @@ class _SyncBuffer(Module):
self.sync += _inc(produce, depth) self.sync += _inc(produce, depth)
rdport = storage.get_port(async_read=True) rdport = storage.get_port(async_read=True)
self.specials += rdport
self.comb += [ self.comb += [
rdport.adr.eq(consume), rdport.adr.eq(consume),
self.dout.eq(rdport.dat_r) self.dout.eq(rdport.dat_r)

1
milkymist/dvisampler/edid.py
View File

@ -89,6 +89,7 @@ class EDID(Module, AutoCSR):
) )
] ]
rdport = self.mem.get_port() rdport = self.mem.get_port()
self.specials += rdport
self.comb += rdport.adr.eq(offset_counter) self.comb += rdport.adr.eq(offset_counter)
data_bit = Signal() data_bit = Signal()

4
top.py
View File

@ -86,8 +86,8 @@ class SoC(Module):
"uart": 0, "uart": 0,
"timer0": 1, "timer0": 1,
"minimac": 2, "minimac": 2,
"dvisampler0": 3, "dvisampler0": 3,
"dvisampler1": 4, "dvisampler1": 4,
} }
def __init__(self, platform): def __init__(self, platform):