for now use our fork of migen (to be able to simulate our designs)

litex/boards/targets/de0nano.py

@@ -2,7 +2,7 @@
 
 import argparse
 
-from migen import *
+from litex.gen import *
 from litex.boards.platforms import de0nano
 
 from litex.soc.cores.sdram.settings import IS42S16160

litex/boards/targets/kc705.py

@@ -2,8 +2,8 @@
 
 import argparse
 
-from migen import *
-from migen.genlib.resetsync import AsyncResetSynchronizer
+from litex.gen import *
+from litex.gen.genlib.resetsync import AsyncResetSynchronizer
 from litex.boards.platforms import kc705
 
 from litex.soc.cores.sdram.settings import MT8JTF12864

litex/boards/targets/minispartan6.py

@@ -3,8 +3,8 @@
 import argparse
 from fractions import Fraction
 
-from migen import *
-from migen.genlib.resetsync import AsyncResetSynchronizer
+from litex.gen import *
+from litex.gen.genlib.resetsync import AsyncResetSynchronizer
 from litex.boards.platforms import minispartan6
 
 from litex.soc.cores.sdram.settings import AS4C16M16

litex/boards/targets/sim.py

@@ -3,9 +3,9 @@
 import argparse
 import importlib
 
-from migen import *
+from litex.gen import *
 from litex.boards.platforms import sim
-from migen.genlib.io import CRG
+from litex.gen.genlib.io import CRG
 
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *

litex/boards/targets/simple.py

@@ -3,8 +3,8 @@
 import argparse
 import importlib
 
-from migen import *
-from migen.genlib.io import CRG
+from litex.gen import *
+from litex.gen.genlib.io import CRG
 
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.builder import *

litex/build/altera/common.py

@@ -1,6 +1,6 @@
-from migen.fhdl.module import Module
-from migen.fhdl.specials import Instance
-from migen.genlib.io import DifferentialInput, DifferentialOutput
+from litex.gen.fhdl.module import Module
+from litex.gen.fhdl.specials import Instance
+from litex.gen.genlib.io import DifferentialInput, DifferentialOutput
 
 
 class AlteraDifferentialInputImpl(Module):

litex/build/altera/quartus.py

@@ -4,7 +4,7 @@
 import os
 import subprocess
 
-from migen.fhdl.structure import _Fragment
+from litex.gen.fhdl.structure import _Fragment
 
 from litex.build.generic_platform import Pins, IOStandard, Misc
 from litex.build import tools

litex/build/generic_platform.py

@@ -1,9 +1,9 @@
 import os
 
-from migen.fhdl.structure import Signal
-from migen.genlib.record import Record
-from migen.genlib.io import CRG
-from migen.fhdl import verilog, edif
+from litex.gen.fhdl.structure import Signal
+from litex.gen.genlib.record import Record
+from litex.gen.genlib.io import CRG
+from litex.gen.fhdl import verilog, edif
 from litex.build import tools
 
 

litex/build/lattice/common.py

@@ -1,7 +1,7 @@
-from migen.fhdl.module import Module
-from migen.fhdl.specials import Instance
-from migen.genlib.io import *
-from migen.genlib.resetsync import AsyncResetSynchronizer
+from litex.gen.fhdl.module import Module
+from litex.gen.fhdl.specials import Instance
+from litex.gen.genlib.io import *
+from litex.gen.genlib.resetsync import AsyncResetSynchronizer
 
 
 class LatticeAsyncResetSynchronizerImpl(Module):

litex/build/lattice/diamond.py

@@ -6,7 +6,7 @@ import sys
 import subprocess
 import shutil
 
-from migen.fhdl.structure import _Fragment
+from litex.gen.fhdl.structure import _Fragment
 
 from litex.build.generic_platform import *
 from litex.build import tools

litex/build/sim/verilator.py

@@ -4,7 +4,7 @@
 import os
 import subprocess
 
-from migen.fhdl.structure import _Fragment
+from litex.gen.fhdl.structure import _Fragment
 from litex.build import tools
 from litex.build.generic_platform import *
 

litex/build/xilinx/common.py

@@ -2,13 +2,13 @@ import os
 import sys
 from distutils.version import StrictVersion
 
-from migen.fhdl.structure import *
-from migen.fhdl.specials import Instance
-from migen.fhdl.module import Module
-from migen.fhdl.specials import SynthesisDirective
-from migen.genlib.cdc import *
-from migen.genlib.resetsync import AsyncResetSynchronizer
-from migen.genlib.io import *
+from litex.gen.fhdl.structure import *
+from litex.gen.fhdl.specials import Instance
+from litex.gen.fhdl.module import Module
+from litex.gen.fhdl.specials import SynthesisDirective
+from litex.gen.genlib.cdc import *
+from litex.gen.genlib.resetsync import AsyncResetSynchronizer
+from litex.gen.genlib.io import *
 
 from litex.build import tools
 

litex/build/xilinx/ise.py

@@ -2,7 +2,7 @@ import os
 import subprocess
 import sys
 
-from migen.fhdl.structure import _Fragment
+from litex.gen.fhdl.structure import _Fragment
 from litex.build.generic_platform import *
 from litex.build import tools
 from litex.build.xilinx import common

litex/build/xilinx/vivado.py

@@ -5,7 +5,7 @@ import os
 import subprocess
 import sys
 
-from migen.fhdl.structure import _Fragment
+from litex.gen.fhdl.structure import _Fragment
 from litex.build.generic_platform import *
 from litex.build import tools
 from litex.build.xilinx import common

litex/gen/fhdl/verilog.py

@@ -144,7 +144,8 @@ def _printnode(ns, at, level, node, target_filter=None):
     elif isinstance(node, Case):
         if node.cases:
             r = "\t"*level + "case (" + _printexpr(ns, node.test)[0] + ")\n"
-            css = sorted([(k, v) for (k, v) in node.cases.items() if k != "default"], key=itemgetter(0))
+            css = [(k, v) for k, v in node.cases.items() if isinstance(k, Constant)]
+            css = sorted(css, key=lambda x: x[0].value)
             for choice, statements in css:
                 r += "\t"*(level + 1) + _printexpr(ns, choice)[0] + ": begin\n"
                 r += _printnode(ns, at, level + 2, statements, target_filter)
@@ -359,7 +360,7 @@ def convert(f, ios=None, name="top",
     ns.clock_domains = f.clock_domains
     r.ns = ns
 
-    src = "/* Machine-generated using Migen */\n"
+    src = "/* Machine-generated using LiteX gen*/\n"
     src += _printheader(f, ios, name, ns,
                         reg_initialization=not asic_syntax)
     src += _printcomb(f, ns,

litex/soc/cores/cpu/lm32/core.py

@@ -1,6 +1,6 @@
 import os
 
-from migen import *
+from litex.gen import *
 
 from litex.soc.interconnect import wishbone
 

litex/soc/cores/cpu/mor1kx/core.py

@@ -1,6 +1,6 @@
 import os
 
-from migen import *
+from litex.gen import *
 
 from litex.soc.interconnect import wishbone
 

litex/soc/cores/flash/nor_flash_16.py

@@ -1,5 +1,5 @@
-from migen import *
-from migen.genlib.fsm import FSM, NextState
+from litex.gen import *
+from litex.gen.genlib.fsm import FSM, NextState
 
 from litex.soc.interconnect import wishbone
 

litex/soc/cores/flash/spi_flash.py

@@ -1,5 +1,5 @@
-from migen import *
-from migen.genlib.misc import timeline
+from litex.gen import *
+from litex.gen.genlib.misc import timeline
 
 from litex.soc.interconnect import wishbone
 from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRStatus

litex/soc/cores/gpio.py

@@ -1,5 +1,5 @@
-from migen import *
-from migen.genlib.cdc import MultiReg
+from litex.gen import *
+from litex.gen.genlib.cdc import MultiReg
 
 from litex.soc.interconnect.csr import *
 

litex/soc/cores/identifier.py

@@ -1,4 +1,4 @@
-from migen import *
+from litex.gen import *
 
 
 class Identifier(Module):

litex/soc/cores/liteeth_mini/common.py

@@ -1,5 +1,5 @@
-from migen import *
-from migen.genlib.record import *
+from litex.gen import *
+from litex.gen.genlib.record import *
 
 from litex.soc.interconnect.csr import *
 from litex.soc.interconnect.stream import *

litex/soc/cores/liteeth_mini/mac/__init__.py

@@ -1,4 +1,4 @@
-from migen import *
+from litex.gen import *
 
 from litex.soc.interconnect.csr import *
 from litex.soc.cores.liteeth_mini.common import *

litex/soc/cores/liteeth_mini/mac/core/__init__.py

@@ -1,4 +1,4 @@
-from migen import *
+from litex.gen import *
 
 from litex.soc.interconnect.csr import *
 from litex.soc.cores.liteeth_mini.common import *

litex/soc/cores/liteeth_mini/mac/core/crc.py

@@ -2,8 +2,8 @@ from collections import OrderedDict
 from functools import reduce
 from operator import xor
 
-from migen import *
-from migen.genlib.misc import chooser
+from litex.gen import *
+from litex.gen.genlib.misc import chooser
 
 from litex.soc.interconnect.stream import *
 

litex/soc/cores/liteeth_mini/mac/core/gap.py

@@ -1,7 +1,7 @@
 import math
 
-from migen import *
-from migen.genlib.fsm import *
+from litex.gen import *
+from litex.gen.genlib.fsm import *
 
 from litex.soc.interconnect.stream import Sink, Source
 from litex.soc.cores.liteeth_mini.common import eth_phy_description, eth_interpacket_gap

litex/soc/cores/liteeth_mini/mac/core/last_be.py

@@ -1,4 +1,4 @@
-from migen import *
+from litex.gen import *
 
 from litex.soc.interconnect.stream import *
 from litex.soc.cores.liteeth_mini.common import eth_phy_description

litex/soc/cores/liteeth_mini/mac/core/padding.py

@@ -1,6 +1,6 @@
 import math
 
-from migen import *
+from litex.gen import *
 
 from litex.soc.interconnect.stream import *
 from litex.soc.cores.liteeth_mini.common import eth_phy_description

litex/soc/cores/liteeth_mini/mac/core/preamble.py

@@ -1,7 +1,7 @@
-from migen import *
-from migen.genlib.fsm import *
-from migen.genlib.misc import chooser
-from migen.genlib.record import Record
+from litex.gen import *
+from litex.gen.genlib.fsm import *
+from litex.gen.genlib.misc import chooser
+from litex.gen.genlib.record import Record
 
 from litex.soc.interconnect.stream import *
 from litex.soc.cores.liteeth_mini.common import eth_phy_description, eth_preamble

litex/soc/cores/liteeth_mini/mac/frontend/wishbone.py

@@ -1,5 +1,5 @@
-from migen import *
-from migen.fhdl.simplify import FullMemoryWE
+from litex.gen import *
+from litex.gen.fhdl.simplify import FullMemoryWE
 
 from litex.soc.interconnect import wishbone
 from litex.soc.interconnect.csr import *

litex/soc/cores/liteeth_mini/phy/gmii.py

@@ -1,6 +1,6 @@
-from migen import *
-from migen.genlib.io import DDROutput
-from migen.genlib.resetsync import AsyncResetSynchronizer
+from litex.gen import *
+from litex.gen.genlib.io import DDROutput
+from litex.gen.genlib.resetsync import AsyncResetSynchronizer
 
 from litex.soc.cores.liteeth_mini.common import *
 

litex/soc/cores/liteeth_mini/phy/gmii_mii.py

@@ -1,6 +1,6 @@
-from migen import *
-from migen.genlib.io import DDROutput
-from migen.genlib.cdc import PulseSynchronizer
+from litex.gen import *
+from litex.gen.genlib.io import DDROutput
+from litex.gen.genlib.cdc import PulseSynchronizer
 
 from litex.soc.interconnect.stream import *
 from litex.soc.cores.liteeth_mini.common import *

litex/soc/cores/liteeth_mini/phy/loopback.py

@@ -1,4 +1,4 @@
-from migen import *
+from litex.gen import *
 
 from litex.soc.interconnect.csr import *
 from litex.soc.interconnect.stream import *

litex/soc/cores/liteeth_mini/phy/mii.py

@@ -1,4 +1,4 @@
-from migen import *
+from litex.gen import *
 
 from litex.soc.interconnect.csr import *
 from litex.soc.interconnect.stream import *

litex/soc/cores/liteeth_mini/phy/s6rgmii.py

@@ -1,9 +1,9 @@
 # RGMII PHY for Spartan-6
 
-from migen import *
-from migen.genlib.io import DDROutput
-from migen.genlib.misc import WaitTimer
-from migen.genlib.fsm import FSM, NextState
+from litex.gen import *
+from litex.gen.genlib.io import DDROutput
+from litex.gen.genlib.misc import WaitTimer
+from litex.gen.genlib.fsm import FSM, NextState
 
 from litex.soc.interconnect.stream import *
 from litex.soc.interconnect.csr import *

litex/soc/cores/sdram/dfii.py

@@ -1,4 +1,4 @@
-from migen import *
+from litex.gen import *
 
 from litex.soc.interconnect import dfi
 from litex.soc.interconnect.csr import *

litex/soc/cores/sdram/lasmicon/bankmachine.py

@@ -1,7 +1,7 @@
-from migen import *
-from migen.genlib.roundrobin import *
-from migen.genlib.fsm import FSM, NextState
-from migen.genlib.fifo import SyncFIFO
+from litex.gen import *
+from litex.gen.genlib.roundrobin import *
+from litex.gen.genlib.fsm import FSM, NextState
+from litex.gen.genlib.fifo import SyncFIFO
 
 from litex.soc.cores.sdram.lasmicon.multiplexer import *
 

litex/soc/cores/sdram/lasmicon/core.py

@@ -1,4 +1,4 @@
-from migen import *
+from litex.gen import *
 
 from litex.soc.interconnect import dfi, lasmi_bus
 from litex.soc.cores.sdram.lasmicon.refresher import *

litex/soc/cores/sdram/lasmicon/multiplexer.py

@@ -1,9 +1,9 @@
 from functools import reduce
 from operator import or_, and_
 
-from migen import *
-from migen.genlib.roundrobin import *
-from migen.genlib.fsm import FSM, NextState
+from litex.gen import *
+from litex.gen.genlib.roundrobin import *
+from litex.gen.genlib.fsm import FSM, NextState
 
 from litex.soc.cores.sdram.lasmicon.perf import Bandwidth
 from litex.soc.interconnect.csr import AutoCSR

litex/soc/cores/sdram/lasmicon/perf.py

@@ -1,4 +1,4 @@
-from migen import *
+from litex.gen import *
 
 from litex.soc.interconnect.csr import *
 

litex/soc/cores/sdram/lasmicon/refresher.py

@@ -1,6 +1,6 @@
-from migen import *
-from migen.genlib.misc import timeline
-from migen.genlib.fsm import FSM
+from litex.gen import *
+from litex.gen.genlib.misc import timeline
+from litex.gen.genlib.fsm import FSM
 
 from litex.soc.cores.sdram.lasmicon.multiplexer import *
 

litex/soc/cores/sdram/minicon/core.py

@@ -1,9 +1,9 @@
 from functools import reduce
 from operator import or_
 
-from migen import *
-from migen.genlib.fsm import FSM, NextState
-from migen.genlib.misc import WaitTimer
+from litex.gen import *
+from litex.gen.genlib.fsm import FSM, NextState
+from litex.gen.genlib.misc import WaitTimer
 
 from litex.soc.interconnect import dfi as dfibus
 from litex.soc.interconnect import wishbone

litex/soc/cores/sdram/model.py

@@ -6,8 +6,8 @@
 # TODO:
 # - add $display support to LiteX gen and manage timing violations?
 
-from migen import *
-from migen.fhdl.specials import *
+from litex.gen import *
+from litex.gen.fhdl.specials import *
 from litex.soc.interconnect.dfi import *
 
 from functools import reduce

litex/soc/cores/sdram/phy/gensdrphy.py

@@ -21,9 +21,9 @@
 # This PHY only supports CAS Latency 2.
 #
 
-from migen import *
-from migen.genlib.record import *
-from migen.fhdl.specials import Tristate
+from litex.gen import *
+from litex.gen.genlib.record import *
+from litex.gen.fhdl.specials import Tristate
 
 from litex.soc.interconnect.dfi import *
 from litex.soc.cores.sdram import settings as sdram_settings

litex/soc/cores/sdram/phy/k7ddrphy.py

@@ -1,6 +1,6 @@
 # tCK=5ns CL=7 CWL=6
 
-from migen import *
+from litex.gen import *
 
 from litex.soc.interconnect.dfi import *
 from litex.soc.interconnect.csr import *

litex/soc/cores/sdram/phy/s6ddrphy.py

@@ -19,8 +19,8 @@
 from functools import reduce
 from operator import or_
 
-from migen import *
-from migen.genlib.record import *
+from litex.gen import *
+from litex.gen.genlib.record import *
 
 from litex.soc.interconnect.dfi import *
 from litex.soc.cores.sdram import settings as sdram_settings

litex/soc/cores/sdram/settings.py

@@ -1,7 +1,7 @@
 from math import ceil
 from collections import namedtuple
 
-from migen import *
+from litex.gen import *
 
 
 PhySettingsT = namedtuple("PhySettings", "memtype dfi_databits nphases rdphase wrphase rdcmdphase wrcmdphase cl cwl read_latency write_latency")

litex/soc/cores/sdram/tester.py

@@ -1,7 +1,7 @@
 from functools import reduce
 from operator import xor
 
-from migen import *
+from litex.gen import *
 
 from litex.soc.interconnect.csr import *
 from litex.soc.interconnect import dma_lasmi
@@ -114,8 +114,8 @@ class _LFSRTB(Module):
         print("{0:032x}".format(selfp.dut.o))
 
 if __name__ == "__main__":
-    from migen.fhdl import verilog
-    from migen.sim.generic import run_simulation
+    from litex.gen.fhdl import verilog
+    from litex.gen.sim.generic import run_simulation
 
     lfsr = LFSR(3, 4, [3, 2])
     print(verilog.convert(lfsr, ios={lfsr.ce, lfsr.reset, lfsr.o}))

litex/soc/cores/spi/core.py

@@ -1,6 +1,6 @@
-from migen import *
-from migen.bank.description import *
-from migen.genlib.fsm import FSM, NextState
+from litex.gen import *
+from litex.gen.bank.description import *
+from litex.gen.genlib.fsm import FSM, NextState
 
 
 class SPIMaster(Module, AutoCSR):

litex/soc/cores/spi/test.py

@@ -1,6 +1,6 @@
-from migen import *
-from migen.genlib.record import *
-from migen.sim.generic import run_simulation
+from litex.gen import *
+from litex.gen.genlib.record import *
+from litex.gen.sim.generic import run_simulation
 
 from litex.soc.com.spi import SPIMaster
 

litex/soc/cores/timer.py

@@ -1,4 +1,4 @@
-from migen import *
+from litex.gen import *
 
 from litex.soc.interconnect.csr import *
 from litex.soc.interconnect.csr_eventmanager import *

litex/soc/cores/uart/bridge.py

@@ -1,4 +1,4 @@
-from migen import *
+from litex.gen import *
 
 from litex.soc.interconnect.wishbonebridge import WishboneStreamingBridge
 from litex.soc.cores.uart.core import RS232PHY

litex/soc/cores/uart/core.py

@@ -1,6 +1,6 @@
-from migen import *
-from migen.genlib.record import Record
-from migen.genlib.cdc import MultiReg
+from litex.gen import *
+from litex.gen.genlib.record import Record
+from litex.gen.genlib.cdc import MultiReg
 
 from litex.soc.interconnect.csr import *
 from litex.soc.interconnect.csr_eventmanager import *

litex/soc/integration/cpu_interface.py

@@ -1,4 +1,4 @@
-from migen import *
+from litex.gen import *
 
 from litex.soc.interconnect.csr import CSRStatus
 

litex/soc/integration/sdram_init.py

@@ -1,4 +1,4 @@
-from migen import log2_int
+from litex.gen import log2_int
 
 
 def get_sdram_phy_header(sdram_phy_settings):

litex/soc/integration/soc_core.py

@@ -1,6 +1,6 @@
 from operator import itemgetter
 
-from migen import *
+from litex.gen import *
 
 from litex.soc.cores import identifier, timer, uart
 from litex.soc.cores.cpu import lm32, mor1kx

litex/soc/integration/soc_sdram.py

@@ -1,5 +1,5 @@
-from migen import *
-from migen.genlib.record import *
+from litex.gen import *
+from litex.gen.genlib.record import *
 
 from litex.soc.interconnect import wishbone, wishbone2lasmi, lasmi_bus
 from litex.soc.interconnect.csr import AutoCSR
@@ -84,7 +84,7 @@ class SoCSDRAM(SoCCore):
                 # Remove this workaround when fixed by Xilinx.
                 from litex.build.xilinx.vivado import XilinxVivadoToolchain
                 if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
-                    from migen.fhdl.simplify import FullMemoryWE
+                    from litex.gen.fhdl.simplify import FullMemoryWE
                     self.submodules.l2_cache = FullMemoryWE()(l2_cache)
                 else:
                     self.submodules.l2_cache = l2_cache
@@ -97,7 +97,7 @@ class SoCSDRAM(SoCCore):
                 # Remove this workaround when fixed by Xilinx.
                 from litex.build.xilinx.vivado import XilinxVivadoToolchain
                 if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
-                    from migen.fhdl.simplify import FullMemoryWE
+                    from litex.gen.fhdl.simplify import FullMemoryWE
                     self.submodules.l2_cache = FullMemoryWE()(l2_cache)
                 else:
                     self.submodules.l2_cache = l2_cache

litex/soc/interconnect/csr.py

@@ -1,6 +1,6 @@
-from migen import *
-from migen.util.misc import xdir
-from migen.fhdl.tracer import get_obj_var_name
+from litex.gen import *
+from litex.gen.util.misc import xdir
+from litex.gen.fhdl.tracer import get_obj_var_name
 
 
 class _CSRBase(DUID):

litex/soc/interconnect/csr_bus.py

@@ -1,7 +1,7 @@
-from migen import *
-from migen.genlib.record import *
-from migen.genlib.misc import chooser
-from migen.util.misc import xdir
+from litex.gen import *
+from litex.gen.genlib.record import *
+from litex.gen.genlib.misc import chooser
+from litex.gen.util.misc import xdir
 
 from litex.soc.interconnect import csr
 from litex.soc.interconnect.csr import CSRStorage

litex/soc/interconnect/csr_eventmanager.py

@@ -1,8 +1,8 @@
 from functools import reduce
 from operator import or_
 
-from migen import *
-from migen.util.misc import xdir
+from litex.gen import *
+from litex.gen.util.misc import xdir
 
 from litex.soc.interconnect.csr import *
 

litex/soc/interconnect/dfi.py

@@ -1,5 +1,5 @@
-from migen import *
-from migen.genlib.record import *
+from litex.gen import *
+from litex.gen.genlib.record import *
 
 
 def phase_cmd_description(addressbits, bankbits):

litex/soc/interconnect/dma_lasmi.py

@@ -1,5 +1,5 @@
-from migen import *
-from migen.genlib.fifo import SyncFIFO
+from litex.gen import *
+from litex.gen.genlib.fifo import SyncFIFO
 
 
 class Reader(Module):

litex/soc/interconnect/lasmi_bus.py

@@ -1,9 +1,9 @@
 from functools import reduce
 from operator import or_
 
-from migen import *
-from migen.genlib import roundrobin
-from migen.genlib.record import *
+from litex.gen import *
+from litex.gen.genlib import roundrobin
+from litex.gen.genlib.record import *
 
 
 class Interface(Record):

litex/soc/interconnect/packet.py

@@ -1,7 +1,7 @@
-from migen import *
-from migen.genlib.roundrobin import *
-from migen.genlib.record import *
-from migen.genlib.fsm import FSM, NextState
+from litex.gen import *
+from litex.gen.genlib.roundrobin import *
+from litex.gen.genlib.record import *
+from litex.gen.genlib.fsm import FSM, NextState
 
 from litex.soc.interconnect.stream import *
 

litex/soc/interconnect/stream.py

@@ -1,6 +1,6 @@
-from migen import *
-from migen.genlib.record import *
-from migen.genlib import fifo
+from litex.gen import *
+from litex.gen.genlib.record import *
+from litex.gen.genlib import fifo
 
 
 def _make_m2s(layout):
@@ -159,7 +159,7 @@ class Demultiplexer(Module):
 # XXX
 
 from copy import copy
-from migen.util.misc import xdir
+from litex.gen.util.misc import xdir
 
 def pack_layout(l, n):
     return [("chunk"+str(i), l) for i in range(n)]

litex/soc/interconnect/wishbone.py

@@ -1,11 +1,11 @@
 from functools import reduce
 from operator import or_
 
-from migen import *
-from migen.genlib import roundrobin
-from migen.genlib.record import *
-from migen.genlib.misc import split, displacer, chooser
-from migen.genlib.fsm import FSM, NextState
+from litex.gen import *
+from litex.gen.genlib import roundrobin
+from litex.gen.genlib.record import *
+from litex.gen.genlib.misc import split, displacer, chooser
+from litex.gen.genlib.fsm import FSM, NextState
 
 from litex.soc.interconnect import csr
 

litex/soc/interconnect/wishbone2csr.py

@@ -1,5 +1,5 @@
-from migen import *
-from migen.genlib.misc import timeline
+from litex.gen import *
+from litex.gen.genlib.misc import timeline
 
 from litex.soc.interconnect import csr_bus, wishbone
 

litex/soc/interconnect/wishbone2lasmi.py

@@ -1,5 +1,5 @@
-from migen import *
-from migen.genlib.fsm import FSM, NextState
+from litex.gen import *
+from litex.gen.genlib.fsm import FSM, NextState
 
 
 class WB2LASMI(Module):

litex/soc/interconnect/wishbonebridge.py

@@ -1,8 +1,8 @@
-from migen import *
+from litex.gen import *
 
-from migen.genlib.misc import chooser, WaitTimer
-from migen.genlib.record import Record
-from migen.genlib.fsm import FSM, NextState
+from litex.gen.genlib.misc import chooser, WaitTimer
+from litex.gen.genlib.record import Record
+from litex.gen.genlib.fsm import FSM, NextState
 
 from litex.soc.interconnect import wishbone
 from litex.soc.interconnect.stream import Sink, Source