Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

global: pep8 (E261, E271)

This commit is contained in:
Florent Kermarrec 2015-04-13 17:16:12 +02:00
parent 71d0f6ab2a
commit fc68d915c1
22 changed files with 72 additions and 72 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
misoc_import.py
View File

@ -5,7 +5,7 @@ import importlib
def misoc_import(default, external, name):
if external:
try:
del sys.modules[name] # force external path search
del sys.modules[name] # force external path search
except KeyError:
pass
loader = importlib.find_loader(name, [external])

6
misoclib/com/uart/phy/serial.py
View File

@ -23,7 +23,7 @@ class UARTPHYSerialRX(Module):
rx_done.eq(0),
rx_r.eq(rx),
If(~rx_busy,
If(~rx & rx_r, # look for start bit
If(~rx & rx_r, # look for start bit
rx_busy.eq(1),
rx_bitcount.eq(0),
)
@ -31,12 +31,12 @@ class UARTPHYSerialRX(Module):
If(uart_clk_rxen,
rx_bitcount.eq(rx_bitcount + 1),
If(rx_bitcount == 0,
If(rx, # verify start bit
If(rx, # verify start bit
rx_busy.eq(0)
)
).Elif(rx_bitcount == 9,
rx_busy.eq(0),
If(rx, # verify stop bit
If(rx, # verify stop bit
rx_data.eq(rx_reg),
rx_done.eq(1)
)

2
misoclib/com/uart/phy/sim.py
View File

@ -24,7 +24,7 @@ class UARTPHYSim(Module):
m, s = pty.openpty()
name = os.ttyname(s)
print("UART tty: "+name)
time.sleep(0.5) # pause for user
time.sleep(0.5) # pause for user
f = open("/tmp/simserial", "w")
f.write(os.ttyname(s))
f.close()

4
misoclib/mem/sdram/core/lasmicon/__init__.py
View File

@ -29,9 +29,9 @@ class LASMIconSettings:
class LASMIcon(Module):
def __init__(self, phy_settings, geom_settings, timing_settings, controller_settings, **kwargs):
if phy_settings.memtype in ["SDR"]:
burst_length = phy_settings.nphases*1 # command multiplication*SDR
burst_length = phy_settings.nphases*1 # command multiplication*SDR
elif phy_settings.memtype in ["DDR", "LPDDR", "DDR2", "DDR3"]:
burst_length = phy_settings.nphases*2 # command multiplication*DDR
burst_length = phy_settings.nphases*2 # command multiplication*DDR
address_align = log2_int(burst_length)
self.dfi = dfi.Interface(geom_settings.addressbits,

4
misoclib/mem/sdram/core/lasmicon/multiplexer.py
View File

@ -115,7 +115,7 @@ class Multiplexer(Module, AutoCSR):
# Command steering
nop = CommandRequest(geom_settings.addressbits, geom_settings.bankbits)
commands = [nop, choose_cmd.cmd, choose_req.cmd, refresher.cmd] # nop must be 1st
commands = [nop, choose_cmd.cmd, choose_req.cmd, refresher.cmd] # nop must be 1st
(STEER_NOP, STEER_CMD, STEER_REQ, STEER_REFRESH) = range(4)
steerer = _Steerer(commands, dfi)
self.submodules += steerer
@ -211,7 +211,7 @@ class Multiplexer(Module, AutoCSR):
steerer.sel[0].eq(STEER_REFRESH),
If(~refresher.req, NextState("READ"))
)
fsm.delayed_enter("RTW", "WRITE", phy_settings.read_latency-1) # FIXME: reduce this, actual limit is around (cl+1)/nphases
fsm.delayed_enter("RTW", "WRITE", phy_settings.read_latency-1) # FIXME: reduce this, actual limit is around (cl+1)/nphases
fsm.delayed_enter("WTR", "READ", timing_settings.tWTR-1)
# FIXME: workaround for zero-delay loop simulation problem with Icarus Verilog
fsm.finalize()

2
misoclib/mem/sdram/core/lasmicon/refresher.py
View File

@ -8,7 +8,7 @@ from misoclib.mem.sdram.core.lasmicon.multiplexer import *
class Refresher(Module):
def __init__(self, a, ba, tRP, tREFI, tRFC, enabled=True):
self.req = Signal()
self.ack = Signal() # 1st command 1 cycle after assertion of ack
self.ack = Signal() # 1st command 1 cycle after assertion of ack
self.cmd = CommandRequest(a, ba)
###

4
misoclib/mem/sdram/core/minicon/__init__.py
View File

@ -44,9 +44,9 @@ class MiniconSettings:
class Minicon(Module):
def __init__(self, phy_settings, geom_settings, timing_settings):
if phy_settings.memtype in ["SDR"]:
burst_length = phy_settings.nphases*1 # command multiplication*SDR
burst_length = phy_settings.nphases*1 # command multiplication*SDR
elif phy_settings.memtype in ["DDR", "LPDDR", "DDR2", "DDR3"]:
burst_length = phy_settings.nphases*2 # command multiplication*DDR
burst_length = phy_settings.nphases*2 # command multiplication*DDR
address_align = log2_int(burst_length)
nbanks = range(2**geom_settings.bankbits)

4
misoclib/mem/sdram/phy/dfii.py
View File

@ -6,7 +6,7 @@ from misoclib.mem.sdram.phy import dfi
class PhaseInjector(Module, AutoCSR):
def __init__(self, phase):
self._command = CSRStorage(6) # cs, we, cas, ras, wren, rden
self._command = CSRStorage(6) # cs, we, cas, ras, wren, rden
self._command_issue = CSR()
self._address = CSRStorage(flen(phase.address))
self._baddress = CSRStorage(flen(phase.bank))
@ -43,7 +43,7 @@ class DFIInjector(Module, AutoCSR):
self.slave = dfi.Interface(addressbits, bankbits, databits, nphases)
self.master = dfi.Interface(addressbits, bankbits, databits, nphases)
self._control = CSRStorage(4) # sel, cke, odt, reset_n
self._control = CSRStorage(4) # sel, cke, odt, reset_n
for n, phase in enumerate(inti.phases):
setattr(self.submodules, "pi" + str(n), PhaseInjector(phase))

6
misoclib/mem/sdram/phy/initsequence.py
View File

@ -187,9 +187,9 @@ const unsigned int sdram_dfii_pix_rddata_addr[{n}] = {{
mr2 |= rtt_wr << 9
return mr2
mr0 = format_mr0(cl, 8, 1) # wr=8 FIXME: this should be ceiling(tWR/tCK)
mr1 = format_mr1(1, 1) # Output Drive Strength RZQ/7 (34 ohm) / Rtt RZQ/4 (60 ohm)
mr2 = format_mr2(sdram_phy_settings.cwl, 2) # Rtt(WR) RZQ/4
mr0 = format_mr0(cl, 8, 1) # wr=8 FIXME: this should be ceiling(tWR/tCK)
mr1 = format_mr1(1, 1) # Output Drive Strength RZQ/7 (34 ohm) / Rtt RZQ/4 (60 ohm)
mr2 = format_mr2(sdram_phy_settings.cwl, 2) # Rtt(WR) RZQ/4
mr3 = 0
init_sequence = [

4
misoclib/mem/sdram/test/lasmicon_df_tb.py
View File

@ -28,12 +28,12 @@ class TB(Module):
def do_simulation(self, selfp):
dfip = selfp.ctler.dfi
for p in dfip.phases:
if p.ras_n and not p.cas_n and not p.we_n: # write
if p.ras_n and not p.cas_n and not p.we_n: # write
d = dfip.phases[0].wrdata | (dfip.phases[1].wrdata << 64)
print(d)
if d != p.address//2 + p.bank*512 + self.open_row*2048:
print("**** ERROR ****")
elif not p.ras_n and p.cas_n and p.we_n: # activate
elif not p.ras_n and p.cas_n and p.we_n: # activate
self.open_row = p.address
if __name__ == "__main__":

2
misoclib/mem/sdram/test/lasmicon_wb.py
View File

@ -9,7 +9,7 @@ from misoclib.mem.sdram.frontend import wishbone2lasmi
from common import sdram_phy, sdram_geom, sdram_timing, DFILogger
l2_size = 8192 # in bytes
l2_size = 8192 # in bytes
def my_generator():

32
misoclib/soc/__init__.py
View File

@ -16,23 +16,23 @@ def mem_decoder(address, start=26, end=29):
class SoC(Module):
csr_map = {
"crg": 0, # user
"uart_phy": 1, # provided by default (optional)
"uart": 2, # provided by default (optional)
"identifier": 3, # provided by default (optional)
"timer0": 4, # provided by default (optional)
"buttons": 5, # user
"leds": 6, # user
"crg": 0, # user
"uart_phy": 1, # provided by default (optional)
"uart": 2, # provided by default (optional)
"identifier": 3, # provided by default (optional)
"timer0": 4, # provided by default (optional)
"buttons": 5, # user
"leds": 6, # user
}
interrupt_map = {
"uart": 0,
"timer0": 1,
"uart": 0,
"timer0": 1,
}
mem_map = {
"rom": 0x00000000, # (shadow @0x80000000)
"sram": 0x10000000, # (shadow @0x90000000)
"main_ram": 0x40000000, # (shadow @0xc0000000)
"csr": 0x60000000, # (shadow @0xe0000000)
"rom": 0x00000000, # (shadow @0x80000000)
"sram": 0x10000000, # (shadow @0x90000000)
"main_ram": 0x40000000, # (shadow @0xc0000000)
"csr": 0x60000000, # (shadow @0xe0000000)
}
def __init__(self, platform, clk_freq,
cpu_type="lm32", cpu_reset_address=0x00000000,
@ -64,9 +64,9 @@ class SoC(Module):
self.csr_data_width = csr_data_width
self.csr_address_width = csr_address_width
self._memory_regions = [] # list of (name, origin, length)
self._csr_regions = [] # list of (name, origin, busword, csr_list/Memory)
self._constants = [] # list of (name, value)
self._memory_regions = [] # list of (name, origin, length)
self._csr_regions = [] # list of (name, origin, busword, csr_list/Memory)
self._constants = [] # list of (name, value)
self._wb_masters = []
self._wb_slaves = []

2
misoclib/video/dvisampler/analysis.py
View File

@ -139,7 +139,7 @@ class FrameExtraction(Module, AutoCSR):
encoded_pixel = Signal(24)
self.comb += encoded_pixel.eq(Cat(self.b, self.g, self.r))
pack_factor = word_width//24
assert(pack_factor & (pack_factor - 1) == 0) # only support powers of 2
assert(pack_factor & (pack_factor - 1) == 0) # only support powers of 2
pack_counter = Signal(max=pack_factor)
self.sync.pix += [
cur_word_valid.eq(0),

6
misoclib/video/dvisampler/clocking.py
View File

@ -40,9 +40,9 @@ class Clocking(Module, AutoCSR):
)
self.specials += Instance("PLL_ADV",
p_CLKFBOUT_MULT=10,
p_CLKOUT0_DIVIDE=1, # pix10x
p_CLKOUT1_DIVIDE=5, # pix2x
p_CLKOUT2_DIVIDE=10, # pix
p_CLKOUT0_DIVIDE=1, # pix10x
p_CLKOUT1_DIVIDE=5, # pix2x
p_CLKOUT2_DIVIDE=10, # pix
p_COMPENSATION="INTERNAL",
i_CLKINSEL=1,

8
misoclib/video/framebuffer/phy.py
View File

@ -33,7 +33,7 @@ class _FIFO(Module):
]
unpack_counter = Signal(max=pack_factor)
assert(pack_factor & (pack_factor - 1) == 0) # only support powers of 2
assert(pack_factor & (pack_factor - 1) == 0) # only support powers of 2
self.sync.pix += [
unpack_counter.eq(unpack_counter + 1),
self.pix_hsync.eq(fifo.dout.hsync),
@ -143,9 +143,9 @@ class _Clocking(Module, AutoCSR):
self.specials += [
Instance("PLL_ADV",
p_CLKFBOUT_MULT=10,
p_CLKOUT0_DIVIDE=1, # pix10x
p_CLKOUT1_DIVIDE=5, # pix2x
p_CLKOUT2_DIVIDE=10, # pix
p_CLKOUT0_DIVIDE=1, # pix10x
p_CLKOUT1_DIVIDE=5, # pix2x
p_CLKOUT2_DIVIDE=10, # pix
p_COMPENSATION="INTERNAL",
i_CLKINSEL=1,

12
targets/kc705.py
View File

@ -73,8 +73,8 @@ class BaseSoC(SDRAMSoC):
default_platform = "kc705"
csr_map = {
"spiflash": 16,
"ddrphy": 17,
"spiflash": 16,
"ddrphy": 17,
}
csr_map.update(SDRAMSoC.csr_map)
@ -103,18 +103,18 @@ class BaseSoC(SDRAMSoC):
class MiniSoC(BaseSoC):
csr_map = {
"ethphy": 18,
"ethmac": 19,
"ethphy": 18,
"ethmac": 19,
}
csr_map.update(BaseSoC.csr_map)
interrupt_map = {
"ethmac": 2,
"ethmac": 2,
}
interrupt_map.update(BaseSoC.interrupt_map)
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
"ethmac": 0x30000000, # (shadow @0xb0000000)
}
mem_map.update(BaseSoC.mem_map)

4
targets/minispartan6.py
View File

@ -46,8 +46,8 @@ class _CRG(Module):
p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=p//1,
p_CLKOUT2_PHASE=0., p_CLKOUT2_DIVIDE=p//1,
p_CLKOUT3_PHASE=0., p_CLKOUT3_DIVIDE=p//1,
p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=p//1, # sys
p_CLKOUT5_PHASE=270., p_CLKOUT5_DIVIDE=p//1, # sys_ps
p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=p//1, # sys
p_CLKOUT5_PHASE=270., p_CLKOUT5_DIVIDE=p//1, # sys_ps
)
self.specials += Instance("BUFG", i_I=pll[4], o_O=self.cd_sys.clk)
self.specials += Instance("BUFG", i_I=pll[5], o_O=self.cd_sys_ps.clk)

12
targets/mlabs_video.py
View File

@ -33,7 +33,7 @@ class _MXClockPads:
class BaseSoC(SDRAMSoC):
default_platform = "mixxeo" # also supports m1
default_platform = "mixxeo" # also supports m1
def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
SDRAMSoC.__init__(self, platform,
@ -69,18 +69,18 @@ INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3";
class MiniSoC(BaseSoC):
csr_map = {
"ethphy": 16,
"ethmac": 17,
"ethphy": 16,
"ethmac": 17,
}
csr_map.update(BaseSoC.csr_map)
interrupt_map = {
"ethmac": 2,
"ethmac": 2,
}
interrupt_map.update(BaseSoC.interrupt_map)
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
"ethmac": 0x30000000, # (shadow @0xb0000000)
}
mem_map.update(BaseSoC.mem_map)
@ -126,7 +126,7 @@ TIMESPEC "TSise_sucks2" = FROM "GRPsys_clk" TO "GRPvga_clk" TIG;
class FramebufferSoC(MiniSoC):
csr_map = {
"fb": 18,
"fb": 18,
}
csr_map.update(MiniSoC.csr_map)

12
targets/pipistrello.py
View File

@ -49,12 +49,12 @@ class _CRG(Module):
o_CLKOUT3=pll[3], p_CLKOUT3_DUTY_CYCLE=.5,
o_CLKOUT4=pll[4], p_CLKOUT4_DUTY_CYCLE=.5,
o_CLKOUT5=pll[5], p_CLKOUT5_DUTY_CYCLE=.5,
p_CLKOUT0_PHASE=0., p_CLKOUT0_DIVIDE=p//4, # sdram wr rd
p_CLKOUT0_PHASE=0., p_CLKOUT0_DIVIDE=p//4, # sdram wr rd
p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=p//8,
p_CLKOUT2_PHASE=270., p_CLKOUT2_DIVIDE=p//2, # sdram dqs adr ctrl
p_CLKOUT3_PHASE=250., p_CLKOUT3_DIVIDE=p//2, # off-chip ddr
p_CLKOUT2_PHASE=270., p_CLKOUT2_DIVIDE=p//2, # sdram dqs adr ctrl
p_CLKOUT3_PHASE=250., p_CLKOUT3_DIVIDE=p//2, # off-chip ddr
p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=p//1,
p_CLKOUT5_PHASE=0., p_CLKOUT5_DIVIDE=p//1, # sys
p_CLKOUT5_PHASE=0., p_CLKOUT5_DIVIDE=p//1, # sys
)
self.specials += Instance("BUFG", i_I=pll[5], o_O=self.cd_sys.clk)
reset = platform.request("user_btn")
@ -92,14 +92,14 @@ class BaseSoC(SDRAMSoC):
default_platform = "pipistrello"
csr_map = {
"spiflash": 16,
"spiflash": 16,
}
csr_map.update(SDRAMSoC.csr_map)
def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
clk_freq = 75*1000000
SDRAMSoC.__init__(self, platform, clk_freq,
cpu_reset_address=0x170000, # 1.5 MB
cpu_reset_address=0x170000, # 1.5 MB
sdram_controller_settings=sdram_controller_settings,
**kwargs)

6
targets/ppro.py
View File

@ -47,8 +47,8 @@ class _CRG(Module):
p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=p//1,
p_CLKOUT2_PHASE=0., p_CLKOUT2_DIVIDE=p//1,
p_CLKOUT3_PHASE=0., p_CLKOUT3_DIVIDE=p//1,
p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=p//1, # sys
p_CLKOUT5_PHASE=270., p_CLKOUT5_DIVIDE=p//1, # sys_ps
p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=p//1, # sys
p_CLKOUT5_PHASE=270., p_CLKOUT5_DIVIDE=p//1, # sys_ps
)
self.specials += Instance("BUFG", i_I=pll[4], o_O=self.cd_sys.clk)
self.specials += Instance("BUFG", i_I=pll[5], o_O=self.cd_sys_ps.clk)
@ -65,7 +65,7 @@ class BaseSoC(SDRAMSoC):
default_platform = "papilio_pro"
csr_map = {
"spiflash": 16,
"spiflash": 16,
}
csr_map.update(SDRAMSoC.csr_map)

8
targets/simple.py
View File

@ -19,18 +19,18 @@ class BaseSoC(SoC):
class MiniSoC(BaseSoC):
csr_map = {
"ethphy": 20,
"ethmac": 21
"ethphy": 20,
"ethmac": 21
}
csr_map.update(BaseSoC.csr_map)
interrupt_map = {
"ethmac": 2,
"ethmac": 2,
}
interrupt_map.update(BaseSoC.interrupt_map)
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
"ethmac": 0x30000000, # (shadow @0xb0000000)
}
mem_map.update(BaseSoC.mem_map)

2
tools/flterm.py
View File

@ -120,7 +120,7 @@ class Flterm:
self.serial = serial.Serial(port, speed, timeout=0.25)
self.serial.flushOutput()
self.serial.flushInput()
self.serial.close() # in case port was not correctly closed
self.serial.close() # in case port was not correctly closed
self.serial.open()
def close(self):