generate linker memory map, move all generated files into the same folder

.gitignore

@@ -9,8 +9,8 @@ build/*
 tools/flterm
 tools/mkmscimg
 tools/byteswap
-software/include/hw/csr.h
-software/include/hw/sdram_phy.h
+software/include/generated/*.h
+software/include/generated/*.ld
 software/videomixer/dvisampler0.c
 software/videomixer/dvisampler0.h
 software/videomixer/dvisampler1.c

make.py

@@ -65,10 +65,12 @@ def main():
  */
 
 """.format(args.platform, args.target, top_class.__name__)
+		linker_header = cpuif.get_linker_regions(soc.cpu_memory_regions)
+		write_to_file("software/include/generated/regions.ld", boilerplate + linker_header)
 		csr_header = cpuif.get_csr_header(soc.csr_base, soc.csrbankarray, soc.interrupt_map)
-		write_to_file("software/include/hw/csr.h", boilerplate + csr_header)
+		write_to_file("software/include/generated/csr.h", boilerplate + csr_header)
 		sdram_phy_header = initsequence.get_sdram_phy_header(soc.ddrphy)
-		write_to_file("software/include/hw/sdram_phy.h", boilerplate + sdram_phy_header)
+		write_to_file("software/include/generated/sdram_phy.h", boilerplate + sdram_phy_header)
 	if args.csr_csv:
 		csr_csv = cpuif.get_csr_csv(soc.csr_base, soc.csrbankarray)
 		write_to_file(args.csr_csv, csr_csv)

misoclib/gensoc/__init__.py

@@ -29,13 +29,14 @@ class GenSoC(Module):
 		"m1":		0x4D31
 	})
 
-	def __init__(self, platform, clk_freq, sram_size, l2_size=0):
+	def __init__(self, platform, clk_freq, cpu_reset_address, sram_size, l2_size=0):
 		self.clk_freq = clk_freq
 		self.sram_size = sram_size
 		self.l2_size = l2_size
+		self.cpu_memory_regions = []
 
 		# Wishbone
-		self.submodules.cpu = lm32.LM32()
+		self.submodules.cpu = lm32.LM32() # TODO: cpu_reset_address
 		self.submodules.sram = wishbone.SRAM(sram_size)
 		self.submodules.wishbone2csr = wishbone2csr.WB2CSR()
 
@@ -47,6 +48,8 @@ class GenSoC(Module):
 			(lambda a: a[26:29] == 1, self.sram.bus),
 			(lambda a: a[27:29] == 3, self.wishbone2csr.wishbone)
 		]
+		self.add_cpu_memory_region("rom", cpu_reset_address, 0x8000) # 32KB for BIOS
+		self.add_cpu_memory_region("sram", 0x10000000, sram_size)
 
 		# CSR
 		self.submodules.uart = uart.UART(platform.request("serial"), clk_freq, baud=115200)
@@ -74,6 +77,9 @@ class GenSoC(Module):
 			raise FinalizeError
 		self._wb_slaves.append((address_decoder, interface))
 
+	def add_cpu_memory_region(self, name, origin, length):
+		self.cpu_memory_regions.append((name, origin, length))
+
 	def do_finalize(self):
 		# Wishbone
 		self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters,
@@ -104,8 +110,8 @@ class SDRAMSoC(GenSoC):
 	}
 	csr_map.update(GenSoC.csr_map)
 
-	def __init__(self, platform, clk_freq, sram_size, l2_size, with_memtest):
-		GenSoC.__init__(self, platform, clk_freq, sram_size, l2_size)
+	def __init__(self, platform, clk_freq, cpu_reset_address, sram_size, l2_size, with_memtest):
+		GenSoC.__init__(self, platform, clk_freq, cpu_reset_address, sram_size, l2_size)
 		self.with_memtest = with_memtest
 		self._sdram_modules_created = False
 
@@ -132,6 +138,8 @@ class SDRAMSoC(GenSoC):
 		# Wishbone bridge: map SDRAM at 0x40000000 (shadow @0xc0000000)
 		self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_size//4, self.lasmixbar.get_master())
 		self.add_wb_slave(lambda a: a[27:29] == 2, self.wishbone2lasmi.wishbone)
+		self.add_cpu_memory_region("sdram", 0x40000000,
+			2**self.lasmicon.lasmic.aw*self.lasmicon.lasmic.dw*self.lasmicon.lasmic.nbanks//8)
 
 	def do_finalize(self):
 		if not self._sdram_modules_created:

misoclib/gensoc/cpuif.py

@@ -1,5 +1,12 @@
 from migen.bank.description import CSRStatus
 
+def get_linker_regions(regions):
+	r = "MEMORY {\n"
+	for name, origin, length in regions:
+		r += "\t{} : ORIGIN = 0x{:08x}, LENGTH = 0x{:08x}\n".format(name, origin, length)
+	r += "}\n"
+	return r
+
 def _get_rw_functions(reg_name, reg_base, size, read_only):
 	r = ""
 
@@ -39,7 +46,7 @@ def _get_rw_functions(reg_name, reg_base, size, read_only):
 	return r
 
 def get_csr_header(csr_base, bank_array, interrupt_map):
-	r = "#ifndef __HW_CSR_H\n#define __HW_CSR_H\n#include <hw/common.h>\n"
+	r = "#ifndef __GENERATED_CSR_H\n#define __GENERATED_CSR_H\n#include <hw/common.h>\n"
 	for name, csrs, mapaddr, rmap in bank_array.banks:
 		r += "\n/* "+name+" */\n"
 		reg_base = csr_base + 0x800*mapaddr

misoclib/s6ddrphy/initsequence.py

@@ -4,8 +4,8 @@ def get_sdram_phy_header(sdram_phy):
 	if sdram_phy.phy_settings.memtype not in ["SDR", "DDR", "LPDDR", "DDR2"]:
 		raise NotImplementedError("The SDRAM PHY header generator only supports SDR, DDR, LPDDR and DDR2")
 
-	r = "#ifndef __HW_SDRAM_PHY_H\n#define __HW_SDRAM_PHY_H\n"
-	r += "#include <hw/common.h>\n#include <hw/csr.h>\n#include <hw/flags.h>\n\n"
+	r = "#ifndef __GENERATED_SDRAM_PHY_H\n#define __GENERATED_SDRAM_PHY_H\n"
+	r += "#include <hw/common.h>\n#include <generated/csr.h>\n#include <hw/flags.h>\n\n"
 
 	r += "static void cdelay(int i);\n"
 

software/bios/boot.c

@@ -8,7 +8,7 @@
 #include <irq.h>
 
 #include <hw/mem.h>
-#include <hw/csr.h>
+#include <generated/csr.h>
 
 #include <net/microudp.h>
 #include <net/tftp.h>

software/bios/isr.c

@@ -1,4 +1,4 @@
-#include <hw/csr.h>
+#include <generated/csr.h>
 #include <irq.h>
 #include <uart.h>
 

software/bios/linker.ld

@@ -3,10 +3,7 @@ ENTRY(_start)
 
 __DYNAMIC = 0;
 
-MEMORY {
-	rom  : ORIGIN = 0x00180000, LENGTH = 0x20000 /* 128K */
-	sram : ORIGIN = 0x10000000, LENGTH = 0x01000 /* 4K */
-}
+INCLUDE generated/regions.ld
 
 SECTIONS
 {

software/bios/main.c

@@ -8,7 +8,7 @@
 #include <irq.h>
 #include <crc.h>
 
-#include <hw/csr.h>
+#include <generated/csr.h>
 #include <hw/mem.h>
 #include <net/microudp.h>
 

software/bios/sdram.c

@@ -1,8 +1,8 @@
 #include <stdio.h>
 #include <stdlib.h>
 
-#include <hw/csr.h>
-#include <hw/sdram_phy.h>
+#include <generated/csr.h>
+#include <generated/sdram_phy.h>
 #include <hw/flags.h>
 #include <hw/mem.h>
 

software/common.mak

@@ -45,7 +45,7 @@ COMMONFLAGS = -Os -mbarrel-shift-enabled -mmultiply-enabled -mdivide-enabled -ms
 	-Wall -fno-builtin -nostdinc -DGIT_ID=$(GIT_ID) $(INCLUDES)
 CFLAGS = $(COMMONFLAGS) -Wstrict-prototypes -Wold-style-definition -Wmissing-prototypes
 CXXFLAGS = $(COMMONFLAGS) -fno-exceptions -ffreestanding
-LDFLAGS = -nostdlib -nodefaultlibs
+LDFLAGS = -nostdlib -nodefaultlibs -L$(MSCDIR)/software/include
 
 # compile and generate dependencies, based on
 # http://scottmcpeak.com/autodepend/autodepend.html

software/libbase/id.c

@@ -1,4 +1,4 @@
-#include <hw/csr.h>
+#include <generated/csr.h>
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>

software/libbase/linker-sdram.ld

@@ -3,9 +3,7 @@ ENTRY(_start)
 
 __DYNAMIC = 0;
 
-MEMORY {
-	sdram  : ORIGIN = 0x40000000, LENGTH = 0x08000000 /* 128M */
-}
+INCLUDE generated/regions.ld
 
 SECTIONS
 {

software/libbase/system.c

@@ -3,7 +3,7 @@
 
 #include <system.h>
 #include <hw/mem.h>
-#include <hw/csr.h>
+#include <generated/csr.h>
 
 void flush_cpu_icache(void)
 {

software/libbase/time.c

@@ -1,4 +1,4 @@
-#include <hw/csr.h>
+#include <generated/csr.h>
 #include <time.h>
 
 void time_init(void)

software/libbase/uart.c

@@ -1,6 +1,6 @@
 #include <uart.h>
 #include <irq.h>
-#include <hw/csr.h>
+#include <generated/csr.h>
 #include <hw/flags.h>
 
 /*

software/libnet/microudp.c

@@ -1,7 +1,7 @@
 #include <stdio.h>
 #include <system.h>
 #include <crc.h>
-#include <hw/csr.h>
+#include <generated/csr.h>
 #include <hw/flags.h>
 #include <hw/mem.h>
 

software/memtest/isr.c

@@ -1,4 +1,4 @@
-#include <hw/csr.h>
+#include <generated/csr.h>
 #include <irq.h>
 #include <uart.h>
 

software/memtest/main.c

@@ -4,7 +4,7 @@
 #include <irq.h>
 #include <uart.h>
 #include <time.h>
-#include <hw/csr.h>
+#include <generated/csr.h>
 #include <hw/flags.h>
 #include <console.h>
 #include <system.h>

software/videomixer/ci.c

@@ -1,7 +1,7 @@
 #include <stdio.h>
 
 #include <console.h>
-#include <hw/csr.h>
+#include <generated/csr.h>
 
 #include "dvisampler0.h"
 #include "dvisampler1.h"

software/videomixer/dvisamplerX.c

@@ -6,7 +6,7 @@
 #include <uart.h>
 #include <time.h>
 #include <system.h>
-#include <hw/csr.h>
+#include <generated/csr.h>
 #include <hw/flags.h>
 
 #include "dvisamplerX.h"

software/videomixer/isr.c

@@ -1,4 +1,4 @@
-#include <hw/csr.h>
+#include <generated/csr.h>
 #include <irq.h>
 #include <uart.h>
 

software/videomixer/main.c

@@ -4,7 +4,7 @@
 #include <irq.h>
 #include <uart.h>
 #include <time.h>
-#include <hw/csr.h>
+#include <generated/csr.h>
 #include <hw/flags.h>
 #include <console.h>
 

software/videomixer/pll.c

@@ -1,5 +1,5 @@
 #include <stdio.h>
-#include <hw/csr.h>
+#include <generated/csr.h>
 
 #include "pll.h"
 

software/videomixer/processor.c

@@ -1,7 +1,7 @@
 #include <stdio.h>
 #include <stdlib.h>
 
-#include <hw/csr.h>
+#include <generated/csr.h>
 #include <hw/flags.h>
 
 #include "dvisampler0.h"

targets/mlabs_video.py

@@ -45,6 +45,7 @@ class MiniSoC(SDRAMSoC):
 	def __init__(self, platform, with_memtest=False):
 		SDRAMSoC.__init__(self, platform,
 			clk_freq=(83 + Fraction(1, 3))*1000000,
+			cpu_reset_address=0x00180000,
 			sram_size=4096,
 			l2_size=8192,
 			with_memtest=with_memtest)